NH82801GR S L8FY Intel, NH82801GR S L8FY Datasheet - Page 9

• Manufacturer Part Number: NH82801GR S L8FY
• Manufacturer: Intel

Specifications of NH82801GR S L8FY

• Lead Free Status / RoHS Status: Compliant

Tables
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet
3-1
4-1
4-2
4-3
5-1
6-1
7-1
8-1
8-2
8-3
8-4
8-5
8-6
9-1
9-2
9-3
9-4
9-5
9-6
9-7
10-1 Absolute Maximum Ratings ............................................................................... 173
10-2 Non Memory Power Characteristics .................................................................... 174
10-3 DDR2 Power Characteristics .............................................................................. 174
10-4 Signal Groups ................................................................................................. 175
10-5 DC Characteristics ........................................................................................... 177
12-1 Complimentary Pins to Drive ............................................................................. 205
12-2 XOR Chain Outputs .......................................................................................... 206
12-3 XOR Chain #0................................................................................................. 207
12-4 XOR Chain #1................................................................................................. 209
12-5 XOR Chain #2................................................................................................. 210
12-6 XOR Chain #3................................................................................................. 211
12-7 XOR Chain #4................................................................................................. 212
12-8 XOR Chain #5................................................................................................. 213
12-9 XOR Chain #6................................................................................................. 214
12-10 XOR Chain #7................................................................................................. 215
12-11 XOR Chain #8................................................................................................. 216
12-12 XOR Chain #9................................................................................................. 218
12-13 XOR Pad Exclusion List ..................................................................................... 218
Device Number Assignment for Internal MCH Devices............................................. 37
Host Bridge Register Address Map (D0:F0) ........................................................... 45
MCHBAR Register Address Map ........................................................................... 71
Egress Port Register Address Map ........................................................................ 82
Host-PCI Express Bridge Register Address Map (D1:F0) .......................................... 87
Host-PCI Express Bridge Register Address Map (D3:F0) ........................................ 129
DMI Register Address Map ................................................................................ 135
Expansion Area Memory Segments .................................................................... 148
Extended System BIOS Area Memory Segments .................................................. 148
System BIOS Area Memory Segments ................................................................ 148
Pre-Allocated Memory Example for 64 MB DRAM, 1 MB VGA and 1 MB TSEG............ 150
SMM Space Table ............................................................................................ 156
SMM Control Table .......................................................................................... 157
Sample System Memory Organization with Interleaved Channels ........................... 160
Sample System Memory Organization with Asymmetric Channels .......................... 160
DDR2 DIMM Supported Configurations ............................................................... 163
DRAM Address Translation (Single/Dual Channel Asymmetric Mode)....................... 163
DRAM Address Translation (Dual Channel Interleaved Mode) ................................. 164
Lane Mapping Configurations ............................................................................ 166
Strap Combinations ......................................................................................... 168
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