NH82801GR S L8FY Intel, NH82801GR S L8FY Datasheet - Page 5

• Manufacturer Part Number: NH82801GR S L8FY
• Manufacturer: Intel

Specifications of NH82801GR S L8FY

• Lead Free Status / RoHS Status: Compliant

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Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet
Host-PCI Express Bridge Registers (D1:F0) .................................................................... 87
5.1
4.3.4
4.3.5
4.3.6
4.3.7
Configuration Register Details (D1:F0) ................................................................. 90
5.1.1
5.1.2
5.1.3
5.1.4
5.1.5
5.1.6
5.1.7
5.1.8
5.1.9
5.1.10 SBUSN1—Secondary Bus Number (D1:F0)................................................. 94
5.1.11 SUBUSN1—Subordinate Bus Number (D1:F0) ............................................ 95
5.1.12 IOBASE1—I/O Base Address (D1:F0) ........................................................ 95
5.1.13 IOLIMIT1—I/O Limit Address (D1:F0) ....................................................... 95
5.1.14 SSTS1—Secondary Status (D1:F0) ........................................................... 96
5.1.15 MBASE1—Memory Base Address (D1:F0)................................................... 97
5.1.16 MLIMIT1—Memory Limit Address (D1:F0) .................................................. 97
5.1.17 PMBASE1—Prefetchable Memory Base Address (D1:F0) ............................... 98
5.1.18 PMLIMIT1—Prefetchable Memory Limit Address (D1:F0) .............................. 98
5.1.19 PMBASEU1—Prefetchable Memory Base Address ......................................... 99
5.1.20 PMLIMITU1—Prefetchable Memory Limit Address ........................................ 99
5.1.21 CAPPTR1—Capabilities Pointer (D1:F0) .................................................... 100
5.1.22 INTRLINE1—Interrupt Line (D1:F0)......................................................... 100
5.1.23 INTRPIN1—Interrupt Pin (D1:F0)............................................................ 101
5.1.24 BCTRL1—Bridge Control (D1:F0) ............................................................ 101
5.1.25 PM_CAPID1—Power Management Capabilities (D1:F0)............................... 102
5.1.26 PM_CS1—Power Management Control/Status (D1:F0) ............................... 103
5.1.27 SS_CAPID—Subsystem ID and Vendor ID Capabilities (D1:F0) ................... 104
5.1.28 SS—Subsystem ID and Subsystem Vendor ID (D1:F0) .............................. 104
5.1.29 MSI_CAPID—Message Signaled Interrupts Capability ID (D1:F0)................. 104
5.1.30 MC—Message Control (D1:F0)................................................................ 105
5.1.31 MA—Message Address (D1:F0)............................................................... 106
5.1.32 MD—Message Data (D1:F0) ................................................................... 106
5.1.33 PCI_EXPRESS_CAPL—PCI Express Link Capability List (D1:F0) ................... 106
5.1.34 PCI_EXPRESS_CAP—PCI Express Link Capabilities (D1:F0) ........................ 107
5.1.35 DCAP—Device Capabilities (D1:F0) ......................................................... 107
5.1.36 DCTL—Device Control (D1:F0) ............................................................... 108
5.1.37 DSTS—Device Status (D1:F0) ................................................................ 108
5.1.38 LCAP—Link Capabilities (D1:F0) ............................................................. 109
5.1.39 LCTL—Link Control (D1:F0) ................................................................... 110
5.1.40 LSTS—Link Status (D1:F0) .................................................................... 111
5.1.41 SLOTCAP—Slot Capabilities (D1:F0) ........................................................ 112
5.1.42 SLOTCTL—Slot Control (D1:F0) .............................................................. 113
5.1.43 SLOTSTS—Slot Status (D1:F0) ............................................................... 114
5.1.44 RCTL—Root Control (D1:F0) .................................................................. 114
5.1.45 RSTS—Root Status (D1:F0) ................................................................... 115
5.1.46 PCI_EXPRESS_LC—PCI Express link Legacy Control .................................. 116
5.1.47 VCECH—Virtual Channel Enhanced Capability Header (D1:F0) .................... 116
5.1.48 PVCCAP1—Port VC Capability Register 1 (D1:F0) ...................................... 117
5.1.49 PVCCAP2—Port VC Capability Register 2 (D1:F0) ...................................... 117
5.1.50 PVCCTL—Port VC Control (D1:F0) ........................................................... 118
EPLE2D—EP Link Entry 2 Description......................................................... 84
EPLE2A—EP Link Entry 2 Address ............................................................. 85
EPLE3D-EP Link Entry 3 Description .......................................................... 85
EPLE3A—EP Link Entry 3 Address ............................................................. 86
VID1—Vendor Identification (D1:F0) ......................................................... 90
DID1—Device Identification (D1:F0) ......................................................... 90
PCICMD1—PCI Command (D1:F0) ............................................................ 90
PCISTS1—PCI Status (D1:F0) .................................................................. 92
RID1—Revision Identification (D1:F0) ....................................................... 93
CC1—Class Code (D1:F0) ........................................................................ 93
CL1—Cache Line Size (D1:F0) .................................................................. 93
HDR1—Header Type (D1:F0) ................................................................... 94
PBUSN1—Primary Bus Number (D1:F0)..................................................... 94
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