NH82801GR S L8FY Intel, NH82801GR S L8FY Datasheet - Page 127

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NH82801GR S L8FY

Manufacturer Part Number
NH82801GR S L8FY
Description
Manufacturer
Intel
Datasheet

Specifications of NH82801GR S L8FY

Lead Free Status / RoHS Status
Compliant
Host-PCI Express Bridge Registers (D1:F0)
5.1.66
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet
CEMSK—Correctable Error Mask (D1:F0)
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Controls reporting of individual correctable errors by the device (or logic associated
with this port) to the PCI Express Root Complex. As these errors are not originating on
the other side of a PCI Express link, no PCI Express error message is sent, but the
unmasked error is reported directly to the root control logic. A masked error
(respective bit set to 1 in the mask register) has no action taken. There is a mask bit
per error bit of the Correctable Error Status register.
31:13
11:9
5:1
Bit
12
8
7
6
0
Access &
Default
R/WC/S
R/WC/S
R/WC/S
R/WC/S
R/WC/S
0 b
0 b
0 b
0 b
0 b
Reserved
Replay Timer Timeout Mask
0 = Not Masked
1 = Masked
Reserved
Replay Number Rollover Mask
0 = Not Masked
1 = Masked
Bad DLLP Mask
0 = Not Masked
1 = Masked
Bad TLP Mask
0 = Not Masked
1 = Masked
Reserved
Receiver Error Mask
0 = Not Masked
1 = Masked
0/1/0/MMR
1D4-1D7h
00000000h
RO; R/W/S
32 bits
Description
127

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