NH82801GR S L8FY Intel, NH82801GR S L8FY Datasheet - Page 26

• Manufacturer Part Number: NH82801GR S L8FY
• Manufacturer: Intel

Specifications of NH82801GR S L8FY

• Lead Free Status / RoHS Status: Compliant

2.3
26
DDR2 DRAM Channel B Interface
SDQS_A[8:0]#
SCKE_A[3:0]
SODT_A[3:0]
SCB_B[7:0]
SCLK_B[5:0]
SCLK_B[5:0]#
SCS_B[3:0]#
SMA_B[13:0]
SBS_B[2:0]
SRAS_B#
SCAS_B#
SWE_B#
SDQ_B[63:0]
SDM_B[7:0]
SDQS_B[8:0]
SDQS_B[8:0]#
SCKE_B[3:0]
SODT_B[3:0]
Signal Name
Signal Name
SSTL-1.8
SSTL-1.8
SSTL-1.8
SSTL-1.8
SSTL-1.8
SSTL-1.8
SSTL-1.8
SSTL-1.8
SSTL-1.8
SSTL-1.8
SSTL-1.8
SSTL-1.8
SSTL-1.8
SSTL-1.8
SSTL-1.8
SSTL-1.8
SSTL-1.8
SSTL-1.8
Type
Type
I/O
I/O
I/O
I/O
2x
2x
2x
2x
2x
I/O
O
O
O
O
O
O
O
O
O
O
O
2x
O
O
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet
ECC Check Byte: These signals are used for ECC.
SDRAM Differential Clock: (3 per DIMM) SCLK_B and its
complement SCLK_B# signal make a differential clock pair output.
The crossing of the positive edge of SCLK_B and the negative edge
of its complement SCLK_B# are used to sample the command and
control signals on the SDRAM.
SDRAM Complementary Differential Clock: (3 per DIMM) These
are the complementary Differential DDR2 Clock signals.
Chip Select: (1 per Rank) These signals select particular SDRAM
components during the active state. There is one Chip Select for
each SDRAM rank
Memory Address: These signals are used to provide the
multiplexed row and column address to the SDRAM
Bank Select: These signals define which banks are selected within
each SDRAM rank. DDR2: 1 Gb technology is 8 banks.
Row Address Strobe: This signal is used with SCAS_B# and
SWE_B# (along with SCS_B#) to define the SDRAM commands
Column Address Strobe: This signal is used with SRAS_B# and
SWE_B# (along with SCS_B#) to define the SDRAM commands.
Write Enable: This signal is used with SCAS_B# and SRAS_B#
(along with SCS_B#) to define the SDRAM commands.
Data Lines: SDQ_B signals interface to the SDRAM data bus
Data Mask: When activated during writes, the corresponding data
groups in the SDRAM are masked. There is one SBDM for every
data byte lane.
Data Strobes: For DDR2, SDQS_B and its complement SDQS_B#
make up a differential strobe pair. The data is captured at the
crossing point of SDQS_B and its complement SDQS_B# during
read and write transactions.
Data Strobe Complements: These are the complementary DDR2
strobe signals.
Clock Enable: (1 per Rank) SCKE_B is used to initialize the
SDRAMs during power-up, and to power-down SDRAM ranks.
On Die Termination: These signals are Active On-die Termination
control signals for DDR2 devices.
Data Strobe Complements: These are the complementary DDR2
strobe signals.
Clock Enable: (1 per Rank) SCKE_A is used to initialize the
SDRAMs during power-up, and to power-down SDRAM ranks.
On Die Termination: These signals are Active On-die Termination
control signals for DDR2 devices.
Description
Description
Signal Description