NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 105

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Register Description
3.8.8.1
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
PCICMD[7:2, 0]- Command Register
This register defines the PCI 2.3 compatible command register values applicable to PCI
Express space.
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version: Intel 5000Z Chipset
Device:
Function:
Offset:
Version:
15:11
Bit
10
9
8
7
6
5
4
3
Attr
RW
RW
RW
RV
RO
RO
RO
RO
RO
0, 2-3
0
04h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
04h
4-7
0
04h
Intel 5000P Chipset
Default
0h
0
0
0
0
0
0
0
0
Reserved. (by PCI SIG)
INTxDisable: Interrupt Disable
Controls the ability of the PCI Express port to generate INTx messages.
This bit does not affect the ability of the Intel 5000P Chipset MCH to route
interrupt messages received at the PCI Express port. However, this bit
controls the generation of legacy interrupts to the DMI for PCI Express
errors detected internally in this port (for example, Malformed TLP, CRC
error, completion time out, and so forth) or when receiving root port error
messages or interrupts due to HP/PM events generated in legacy mode
within the Intel 5000P Chipset MCH. Refer to the INTP register in
3.8.8.27, “INTP[7:2,0] - Interrupt Pin Register” on page 120
routing to DMI.
1: Legacy Interrupt mode is disabled
0: Legacy Interrupt mode is enabled
FB2B: Fast Back-to-Back Enable
Not applicable to PCI Express and is hardwired to 0
SERRE: SERR Message Enable
his field handles the reporting of fatal and non-fatal errors by enabling the
error pins ERR[2:0].
1: Th
0: The Intel 5000P Chipset MCH is disabled from generating fatal/non-fatal
errors.
The errors are also enabled by the PEXDE
Section
In addition, for Type 1 configuration space header devices, for example,
Virtual P2P bridge), this bit, when set, enables transmission of
ERR_NONFATAL and ERR_FATAL error messages
Express interface. This bit does not affect the transmission of forwarded
ERR_COR messages. Refer to the Intel 5000P Chipset MCH RAS Error
Model.
IDSELWCC: IDSEL Stepping/Wait Cycle Control
Not applicable to PCI Express. Hardwired to 0.
PERRE: Parity Error Response Enable
When set, this field enables parity checking.
VGAPSE: VGA palette snoop Enable
Not applicable to PCI Express. Hardwired to 0.
MWIEN: Memory Write and Invalidate Enable
Not applicable to PCI Express. Hardwired to 0.
SCE: Special Cycle Enable
Not applicable to PCI Express. Hardwired to 0.
e Intel 5000P Chipset MCH is enabled to send fatal/non-fatal errors.
3.8.11.4.
Description
VCTRL register in
a
forwarded from the PCI
for interrupt
Section
105