NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 190

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

3.8.13.22
3.8.13.23
190
EMASK_INT - Internal Error Mask Register
A ‘0’ in any bit position enables the corresponding error.
ERR2_INT - Internal Error 2 Mask Register
This register enables the signaling of Err[2] when an error flag is set. Note that one and
only one error signal should be enabled in the ERR2_INT, ERR1_INT, ERR0_INT, and
MCERR_INT for each of the corresponding bits.
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
10:8
6:0
Bit
Bit
Bit
7
7
6
5
4
3
2
1
0
7
6
5
4
3
2
ROST
ROST
RWST
RWST
RWST
RWST
RWST
RWST
Attr
RWST
RWST
RWST
RWST
RWST
RWST
RWST
Attr
RV
Attr
RV
16
2
C8h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
16
2
CCh
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
16
2
D2h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Default
Default
Default
000
00h
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Internal Block that detected the Failure
001: VPP_PEX_PORT2-3
010: VPP_PEX_PORT4-7
011: VPP_FBD
101: COH
101: DM
Others: Reserved
Reserved
COH Entry of Failed Location
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
B8Err2Msk: SF Coherency Error for BIL
B7Err2Msk: Multiple ECC error in any of the ways during SF lookup
B6Err2Msk: Single ECC error on SF lookup
B5Err2Msk: Address Map Error
B4Err2Msk: SMBus Virtual Pin Error
B3Err2Msk: Coherency Violation Error for EWB
B8Msk: SF Coherency Error for BIL
B7Msk: Multiple ECC error in any of the ways during SF lookup
B6Msk: Single ECC error on SF lookup
B5Msk: Address Map Error
B4Msk: Virtual Pin Port Error
B3Msk: Coherency Violation Error for EWB
B2Msk: Multi-Tag Hit SF
B1Msk: DM Parity Error
Description
Description
Description
Register Description