NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 352

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

5.12.8.4
5.12.9
Note:
Table 5-16. PCI Express Credit Mapping for Inbound Transactions (Sheet 1 of 2)
352
ACK Time-out
Packets can get “lost” if the packet is corrupted such that the receiver’s physical layer
does not detect the framing symbols properly. Normally, lost packets are detectable
with non-linearly incrementing sequence numbers. A time-out mechanism exists to
detect (and bound) cases where the last packet sent (over a long period of time) was
corrupted. A replay timer bounds the time a retry buffer entry waits for an ACK or NAK.
Refer to the PCI Express Base Specification, Revision 1.0a for details on this
mechanism for the discussion on Retry Management and the recommended timer
values.
Flow Control
The PCI Express mechanism for flow control is credit based and only applies to TLPs.
DLLP packets do not consume any credits. Through initial hardware negotiation and
subsequent updates, a PCI Express transmitter is aware of the credit capabilities of the
interfacing device. A PCI Express requester will never issue a transaction when there
are not enough advertised credits in the other component to support that transaction.
If there are not enough credits, the requester will hold off that transaction until enough
credits free up to support the transaction. If the ordering rules and available credits
allow other subsequent transactions to proceed, the MCH will allow those transactions.
For example, assume that there are no Non-Posted Request Header Credits (NPRH)
credits remaining and a memory write is the next transaction in the queue. PCI Express
ordering rules allow posted writes to pass reads. Therefore, the Intel 5000P Chipset
MCH will issue the memory write. Subsequent memory reads from the source device
must wait until enough NPRH credits free up.
Flow control is orthogonal with packet ACKs.
The PCI Express flow control credit types are described in
Base Specification, Revision 1.0a defines which TLPs are covered by each flow control
type.
Inbound Posted
Request Header
Credits (IPRH)
Inbound Posted
Request Data
Credits (IPRD)
Inbound Non-
Posted Request
Header Credits
(INPRH)
Flow Control
Type
Tracks the number of inbound posted requests the agent is
capable of supporting. Each credit accounts for one posted
request.
Tracks the number of inbound posted data the agent is capable
of supporting. Each credit accounts for up to 16 bytes of data.
Tracks the number of non-posted requests the agent is capable
of supporting. Each credit accounts for one non-posted request.
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
Definition
Table
5-16. The PCI Express
Functional Description
Advertisement
Initial MCH
216(16X)
56(x16)
108(8X)
56(16X)
14 (4x)
54 (4x)
14 (4X)
28(8x)
28(8X)