NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 33

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Signal Description
2.3.2
2.3.3
2.3.4
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
PCI Express Port 0, Enterprise South Bridge Interface
(ESI)
PCI Express port 0 is a x4 port dedicated to providing the ESI link between the Intel
5000P chipset MCH and the Intel 631xESB/632xESB I/O Controller Hub.
PCI Express Port 2
PCI Express port 2 is a x4 port. PCI Express port 2 is combinable with PCI Express port
3 to form a single PCI Express x8 port. Normally port 2 and port 3 are used to increase
the bandwidth between the Intel 5000P Chipset MCH and the Intel 631xESB/632xESB
I/O Controller Hub.
PCI Express Port 3
PCI Express port 3 is combinable with PCI Express port 2 to form a single PCI Express
x8 port. Normally port 2 and port 3 are used to increase the bandwidth between the
Intel 5000P Chipset MCH and the Intel 631xESB/632xESB I/O Controller Hub.
PE0RP[3:0]
PE0RN[3:0]
PE0TP[3:0]
PE0TN[3:0]
PE2RP[3:0]
PE2RN[3:0]
PE2TP[3:0]
PE2TN[3:0]
PE3RP[3:0]
PE3RN[3:0]
PE3TP[3:0]
PE3TN[3:0]
Signal Name
Signal Name
Signal Name
Type
O
O
I
I
Type
Type
O
O
O
O
I
I
I
I
PCI Express Port 2 Positive Phase Inbound: (Receive) Signals
PCI Express Port 2 Negative Phase Inbound: (Receive) Signals
PCI Express Port 2 Positive Phase Outbound: (Transmit) Signals
PCI Express Port 2 Negative Phase Outbound: (Transmit) Signals
PCI Express Port 0 (ESI) Positive Phase Inbound: (Receive) Signals
PCI Express Port 0 (ESI) Negative Phase Inbound: (Receive) Signals
PCI Express Port 0 (ESI) Positive Phase Outbound: (Transmit) Signals
PCI Express Port 0 (ESI) Negative Phase Outbound: (Transmit) Signals
PCI Express Port 3 Positive Phase: Inbound (Receive) Signals
PCI Express Port 3 Negative Phase: Inbound (Receive) Signals
PCI Express Port 3 Positive Phase: Outbound (Transmit) Signals
PCI Express Port 3 Negative Phase: Outbound (Transmit) Signals
Description Reference
Description
Description
33