NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 320

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Note:
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last value. This provides some degree of hysteresis control to allow the DIMMs to cool
further before THRMTHRT jumps back to a larger number (i.e less throttling) at the
junction when the temperature reached T
This scheme helps in reducing the thermal power by limiting the number of activates.
See
During the global window, the Intel 5000P Chipset MCH will broadcast one
configuration write to the DIMMs AMB.UPDATED registers. This write will not be re-
played or re-sent.
A channel fault could drop an AMB.UPDATED write. If the temperature increased during
the previous global window, but had not actually increased during the current global
window, then THRMTHRT will un-necessarily decrease. If the temperature had not
increased during the previous global window, but had actually increased during the
current global window, then THRMTRHT will remain unresponsive to the temperature
increase for one global throttling window. The situation will rectify itself in the next
global throttling window.
1. Staircase Conditioning [THRTCTRL.THRMODE=0]: This method is employed when
2. Step Conditioning (brute force) [THRTCTRL.THRMODE=1]: This method is
1. If there is a sudden temperature spike between from below Tlow to above Tmid by
THRTCTRL.THRMODE=0 and temperature crosses above Tmid . The THRMTHRT
registries capped to THRTMID (starting point) and it uses a linearly increasing (less
aggressive) throttling algorithm to reduce activations and balance performance and
power envelope when temperature rises and falls around Tmid point. Once
THRTMID is reached, if temperature increases further during the next global
window, then THRMTHRT register will be adjusted by the equation THRMTHRT=
MAX(THRMTHRT -2, THRTHI). This produces the staircase effect as shown in Figure
5-10, “Thermal Throttling with THRMHUNT=1” on page 387. If temperature
decreases subsequently but is still greater than Tmid, then the THRMTHRT will
retain its last value. This provides some degree of hysteresis control to allow the
DIMMs to cool further before THRMTHRT jumps back to a larger number (i.e less
throttling) at the junction when the temperature reached Tmid. Refer to the dotted
line in Figure 5-10, “Thermal Throttling with THRMHUNT=1” on page 387. This
scheme helps in reducing the thermal power by limiting the number of activates.
See Figure 5-12, “Thermal throttling Activation Algorithm” on page 389 for further
details.
employed when THRTCTRL.THRMODE=1 and temperature crosses Tmid . The
THRMTHRT register is capped to THRTHI and it provides a greater degree of
throttling by allowing fewer activates to the memory allowing the DIMM to cool
down quicker but at the expense of performance. This can be used to control
sudden temperature surges that moves the envelope from below Tlow to above
Tmid. and stays there for a long period.
setting the THRMTHRT register to THRTMID as a starting point when
THRTCTRL.THRMODE=0. If temperature rose from above Tlow to above Tmid, then
the THRMTHRT will use THRTMID value if THRTCTRL.THRMODE=0; otherwise it will
use THRTHI if THRTCTRL.THRMODE=1. See the right side of Table 5-8 on page 390
for the various modes.
Figure 5-12
for further details.
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
mid
. Refer to the dotted line in
Functional Description
Figure
5-10.