NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 313

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Functional Description
Figure 5-8.
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
Code Layout for Single-Channel Branches
T ransfer 0
T ransfer 1
T ransfer 0
T ransfer 1
P acket 0
P acket 1
T R A N S F E R
0
1
2
3
4
5
6
7
8
9
1
0
1
1
0
1
2
3
4
5
6
7
8
9
1
0
1
1
C
C
C
C
C
S
C
S
A
C
S
C
S
B
D
N
S
S
1
A
S
S
1
B
3
3
F
0
B
y
1
1
C
S
1
A
C
S
1
B
C
S
3
A
C
S
3
B
[7:0]
C B
x8
A
B
D
2
A
D
2
B
F
D
N
B
D
S
1
5
A
0
D
S
1
5
B
0
S
3
1
A
S
3
1
B
0
y
1
0
C
S
A
C
S
B
C
S
A
C
S
B
0
0
2
2
D
S
D
S
A
D
S
D
S
B
D
S
D
S
A
D
S
D
S
B
F
D
0
N
B
y
9
1
4
1
4
3
0
3
0
D
S
A
D
S
B
D
S
3
1
A
D
S
B
1
5
1
5
3
1
x8
D
N
B
D
S
1
2
A
1
3
A
D
S
1
2
B
1
3
B
D
S
2
8
A
2
9
A
D
S
2
8
B
2
9
B
F
0
y
8
D
D
D
D
S
1
4
A
S
1
4
B
S
3
0
A
S
3
0
B
D
S
D
D
S
D
D
S
D
S
A
D
S
D
S
B
F
D
0
N
B
7
S
1
1
A
S
1
1
B
2
7
2
7
y
D
S
A
D
S
B
D
S
A
D
S
B
1
3
1
3
2
9
2
9
x8
D
D
D
N
S
9
A
A
S
9
B
B
D
S
2
5
A
2
6
A
D
S
2
5
B
2
6
B
F
0
B
y
6
1
0
1
0
D IM M C hannel 0
D
S
1
2
A
D
S
1
2
B
D
S
2
8
A
D
S
2
8
B
D
S
D
S
A
D
S
D
S
B
D
S
D
S
F
D
N
B
8
8
D
S
2
4
A
D
S
2
4
B
0
y
5
D
D
D
S
1
1
A
S
1
1
B
S
2
7
A
D
S
2
7
B
x8
D
S
6
A
7
A
D
S
6
B
7
B
D
S
A
A
D
S
B
B
F
D
0
N
B
y
4
2
2
2
3
2
2
2
3
D
S
A
D
S
B
D
S
A
D
1
0
1
0
2
6
S
2
6
B
D
S
D
S
A
D
S
D
S
B
D
S
D
S
D
N
B
5
5
D
S
2
1
A
D
S
2
1
B
F
0
y
3
D
S
9
A
D
S
9
B
D
S
2
5
A
D
S
2
5
B
x8
D Q [71:0]
D
S
3
A
4
A
D
S
3
B
4
B
D
D
F
D
0
N
B
2
S
1
9
A
2
0
A
S
1
9
B
2
0
B
y
D
S
A
D
S
B
D
S
A
D
S
B
8
8
2
4
2
4
D
D
D
D
D
D
D
N
S
S
2
A
S
S
2
B
S
D
S
1
8
A
S
D
S
1
8
B
F
0
B
y
1
D
S
B
D
S
7
A
D
S
7
B
D
S
2
3
A
2
3
x8
D
S
A
A
D
S
B
B
F
D
N
B
0
1
0
1
D
S
1
6
A
1
7
A
D
S
1
6
B
1
7
B
0
y
0
D
D
D
D
S
B
S
6
A
S
6
B
S
2
2
A
2
2
D
S
A
D
S
B
D
S
A
D
S
2
1
B
5
5
2
1
S ignals
y=[P :N ]
x8
F B D
D
S
4
A
D
S
4
B
D
S
2
0
A
D
S
2
0
B
D
S
A
D
S
B
D
S
A
3
3
1
9
D
S
1
9
B
x8
D
S
2
A
D
S
2
B
D
S
1
8
A
D
S
1
8
B
D
D
D
D
D [n+ 2]
D [n+ 3]
S
1
A
S
1
B
S
1
7
A
S
1
7
B
x8
D [128]
D [129]
D [130]
D [131]
D
S
A
D
S
B
D
S
A
D
S
B
D [0]
D [1]
D [2]
D [3]
0
0
1
6
1
6
D [n+1]
D [n]
D ata
B its
D R A M s
F D 0N B y[0]
D S 0
D S 0
D S 0
D S 0
D S 1
D S 1
D S 0
D S 0
D S 0
D S 0
D S 1
D S 1
[0]
[1]
[2]
[3]
[0]
[1]
[4]
[5]
[6]
[7]
[4]
[5]
F
D
N
B
0
y
0
S ignal
F B D
F B D C hannel 0
D [131] D [130] D [129] D [128]
D Q [3]
D S 0
D S 0
[3]
[7]
D Q [2]
D S 0
D S 0
[2]
[6]
D R A M pins
D Q [1]
D S 0
D S 0
[1]
[5]
D Q [0]
D S 0
D S 0
[0]
[4]
313