NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 80

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

80
a. The DMA Engine CCR for device 8 is defined separately in
Notes:
Device
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
15:8
7:0
Bit
a
:0, 2-3, 9
Attr
RO
RO
0
09h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
09h
Intel 5000Z Chipset
4-7
0
09h
Intel 5000P Chipset
16
0, 2
09h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
17
0
09h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
21
0
09h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
22
0
09h
Intel 5000P Chipset
(DEV2-7)
Default
{04h}
{00h}
else
00h
if
Sub-Class.
This field qualifies the Base Class, providing a more detailed specification of the
device function.
For PCI Express Devices 2,3,4,5,6,7 default is 040h, indicating
For all other Devices: 0,9,10,12,14,16,17,18,19 default is 00h, indicating “Host
Bridge”. See footnote
Register-Level Programming Interface.
This field identifies a specific programming interface (if any), that device
independent software can use to interact with the device. There are no such
interfaces defined for “Host Bridge” types, and this field is hardwired to 00h.
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
a,
for DMA Engine device CCR.
Section
Description
3.10.3.
Register Description
“PCI to PCI Bridge”