NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 208
NQ5000P S L9TN
Manufacturer Part Number
NQ5000P S L9TN
Description
Manufacturer
Intel
Datasheet
1.NQ5000P_S_L9TN.pdf
(530 pages)
Specifications of NQ5000P S L9TN
Mounting
Surface Mount
Lead Free Status / RoHS Status
Not Compliant
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3.9.22
3.9.22.1
3.9.22.2
3.9.22.3
208
FB-DIMM Error Registers
FERR_FAT_FBD - FB-DIMM First Fatal Errors
The first fatal error for an FB-DIMM branch is flagged in these registers. Only one flag is
ever set. Lower-numbered branches have higher priority than higher-numbered
branches. Lower-numbered channels have higher priority than higher-numbered
channels. Higher-order error bits within a register have higher priority than lower-order
bits. The FBDChan_Indx field is not an error. This register will display invalid index
channel data until an error has occurred.
NERR_FAT_FBD - FB-DIMM Next Fatal Errors
If an error is already flagged in FERR_FAT_FBD, subsequent and lower-priority fatal
errors are logged in NERR_FAT_FBD.
FERR_NF_FBD - FB-DIMM First Non-Fatal Errors
The first non-fatal error for a FB-DIMM branch is flagged in these registers. Only one
flag is ever set. Lower-numbered branches have higher priority than higher-numbered
branches. Lower-numbered channels have higher priority than higher-numbered
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
31:30
29:28
15:0
27:3
31:3
Bit
Bit
Bit
2
1
0
2
1
0
Attr
RWCST
RWCST
RWCST
RWCST
RWCST
RWCST
RW
Attr
Attr
RV
RV
RV
RV
16
1
94h, 90h, 8Ch
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
16
1
98h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
16
1
9Ch
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Default
0000h
Default
0000000h
Default
0h
0
0
0
00
00
0
0
0
Reserved
M3Err: >Tmid Thermal event with intelligent throttling disabled
M2Err: Northbound CRC error on non-redundant retry
M1Err: Alert on non-redundant retry or fast reset timeout
ADJLIMIT: Adjusted MIR Limit
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
Reserved
FBDChan_Indx: Logs channel in which the error occurred
Reserved
M3Err: >Tmid Thermal event with intelligent throttling disabled
M2Err: Northbound CRC error on non-redundant retry
M1Err: Alert on non-redundant retry or fast reset timeout
Description
Description
Description
Register Description
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