LSI53CF92A LSI, LSI53CF92A Datasheet - Page 105

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LSI53CF92A

Manufacturer Part Number
LSI53CF92A
Description
Manufacturer
LSI
Datasheet

Specifications of LSI53CF92A

Lead Free Status / RoHS Status
Not Compliant

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When the FSC receives the last byte of a Message In phase, it leaves
ACK/ (Acknowledge) asserted on the bus to prevent the target from
sending any more bytes until the initiator decides to accept or reject the
message. If the initiator accepts the command, it issues a
Message Accepted command. If the initiator does not accept the message,
a Set ATN command should be issued before the Message Accepted
command, causing the target to change to Message Out phase. For
non-DMA commands, an empty FIFO means that the last byte has been
sent. For DMA commands, the transfer counter signals the last byte.
If parity checking is enabled and the FSC detects a parity error on an
incoming SCSI byte while in Initiator mode, it automatically asserts ATN/
prior to deasserting ACK/ for the byte that has the error. The one
exception is after a phase change to Synchronous Data In, and is
described as follows.
If the
Synchronous Offset
register is non-zero (synchronous) and the
phase changes to Data In, the DMA interface is immediately disabled and
the reporting of a parity error during Data In phase is delayed. The phase
change to Data In latches the FIFO flags to indicate how many bytes were
in the FIFO (these bytes are lost); clears the FIFO; loads the FIFO with
the first Data In byte; generates an interrupt; and continues to load the
FIFO with incoming Data In bytes as long as the target sends them, but
not more than the specified offset. To continue receiving Data In bytes, the
microprocessor would normally issue the Transfer Information command to
re-enable the DMA interface. If parity checking is enabled and a parity
error occurred on a previous input phase (Message In or Status), then the
parity error flag is set in the
Status
register and ATN/ is set on the
SCSI bus. If a parity error occurred during the Data In phase, the parity bit
is not set nor is ATN/ asserted until after the FSC receives the subsequent
Transfer Information command.
Initiator Command Group
5-13
Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved.

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