LSI53CF92A LSI, LSI53CF92A Datasheet - Page 58

• Manufacturer Part Number: LSI53CF92A
• Manufacturer: LSI

Specifications of LSI53CF92A

• Lead Free Status / RoHS Status: Not Compliant

4-8
Register: 0x03
Command
Read/Write
Register Bank 0 or 1
This register is a two-deep, 8-bit read/write register that gives commands
to the FSC. Up to two commands may be stacked in the Command
register. The second command may be written before the FSC completes
(or even starts) the first. Reset Chip, Reset SCSI Bus, set Attention
Immediate, and Target Stop DMA execute immediately (within four cycles
of being loaded); all others wait for the previous command to complete.
The last executed (or executing) command remains in the Command
register and may be read by the microprocessor. Reading the Command
register has no effect on its contents. The internal sequencer maintains
a working copy of the bottom of the command FIFO. Certain conditions
cause the working copy to be cleared, allowing the next command to fall
through into the sequencer. If an interrupt was pending prior to these
conditions occurring, the command sequencer remains reset until the
Interrupt register is read. These conditions are as follows:
Registers
Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved.
ENDMA
Hardware reset
Software reset
SCSI bus reset
SCSI bus disconnect
Bus-initiated selection or reselection
Select command
Reconnect command if ATN/ is set
Select or Reselect time-out
Target Terminate command
Parity error detected in target mode
Assertion of ATN/ in target mode
7
0
6
0
0
0
Command Code (CC)
Default
0
0
0
0
0