LSI53CF92A LSI, LSI53CF92A Datasheet - Page 112

• Manufacturer Part Number: LSI53CF92A
• Manufacturer: LSI

Specifications of LSI53CF92A

• Lead Free Status / RoHS Status: Not Compliant

Table 5.14
5.5.6 Target Command Complete Sequence
Table 5.15
5.5.7 Disconnect
5-20
Sequence Step
Sequence Step
0 0 0
0 0 1
0 1 0
0 0 0
0 0 1
0 1 0
[2:0]
[2:0]
Target Terminate Sequence
Target Command Complete Sequence
Interrupt Register
Interrupt Register
0 0 0 1 1 0 0 0
0 0 0 1 1 0 0 0
0 0 0 0 1 0 0 0
0 0 0 1 1 0 0 0
0 0 0 1 1 0 0 0
0 0 1 0 1 0 0 0
Table 5.14
This command is similar to Terminate Sequence, but is used for linked
commands. It causes the FSC first to assert Status phase, send one
byte, then assert Message In phase and send one more byte. The
message byte is normally a Command Complete message. If ATN/ is
asserted by the initiator, the Bus Service and Function Complete bits are
set and an interrupt is generated. If ATN/ is not asserted by the initiator,
a function complete interrupt is generated. In either case, the FSC does
not disconnect.
Table 5.15
This command causes the FSC to release all SCSI bus signals except
RST/ (when triggered, RST/ is driven true for approximately 25 s,
depending on CLK frequency and the clock conversion factor). The FSC
returns to the Disconnected state without generating an interrupt.
Command Set
Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved.
[7:0]
[7:0]
lists the Target Terminate sequence.
lists the Target Command Complete sequence.
Interpretation
Sent one status byte; stopped because initiator set ATN/.
Sent status and message bytes; stopped because initiator
set ATN/.
Command Complete Sequence complete.
Interpretation
Sent one status byte; stopped because initiator set ATN/.
Sent status and message bytes; stopped because initiator
set ATN/.
Terminate Sequence complete; disconnected, bus is free.