LSI53CF92A LSI, LSI53CF92A Datasheet - Page 21

• Manufacturer Part Number: LSI53CF92A
• Manufacturer: LSI

Specifications of LSI53CF92A

• Lead Free Status / RoHS Status: Not Compliant

Chapter 2
Functional Description
This chapter is divided into the following sections:
The FSC has a command set that allows it to perform common SCSI
sequences at hardware speed without host intervention. Its on-chip FIFO
may be accessed simultaneously by the SCSI bus and either the
microprocessor or the host DMA controller. All command, data, status,
and message bytes pass through the FIFO on the way to or from the SCSI
bus. Most FSC commands have two versions: DMA and non-DMA. When
DMA instructions are used, data passes between memory and the SCSI
bus with the FIFO acting as temporary storage when the DMA channel is
temporarily shut down by a higher priority event, such as DRAM refresh.
The FIFO also helps speed execution during non-DMA transfers. For
example, in initiator mode, the microprocessor loads the
Command Descriptor Block (CDB) and optionally, one or three message
bytes into the FIFO. It then issues one of several selection commands
and wait for an interrupt. The FSC waits for bus free, arbitrates for the
bus until it acquires it, sends the message bytes followed by the CDB,
then generates an interrupt. Meanwhile, a multitasking host may continue
with other tasks.
LSI53CF92A Fast SCSI Controller
Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved.
Section 2.1, “Typical SCSI Operation”
Section 2.2, “Bus-Initiated Sequences”
Section 2.3, “Parity Checking and Generation”
Section 2.4, “Host Bus Configuration”
Section 2.5, “DMA Operation”
Section 2.6, “SCSI Data Transfer Rates”
Section 2.7, “Chip Reset”
Section 2.8, “SCAM Capabilities”
2-1