LSI53CF92A LSI, LSI53CF92A Datasheet - Page 74

• Manufacturer Part Number: LSI53CF92A
• Manufacturer: LSI

Specifications of LSI53CF92A

• Lead Free Status / RoHS Status: Not Compliant

4-24
Register: 0x08
Configuration 1 (Config 1)
Read/Write
Register Bank 0
This 8-bit read/write register specifies various operating conditions for the
FSC. Any bit pattern written to this register may be read back and should
be identical. The default value of this register is 0x00.
Slow
SRD
PTest
Registers
Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved.
Slow
7
0
SRD
6
0
Slow Cable Mode
Slow cable mode is needed when cabling conditions
cause SCSI bus violations. It compensates for excessive
capacitive loading on the SCSI data signals by inserting
an extra CLK period between data being asserted on the
bus and REQ/ or ACK/ being driven true. This bit is
cleared (0) by hardware reset or the Reset command, but
not SCSI reset.
SCSI Reset Reporting Interrupt Disable
This bit disables the reporting of a SCSI reset. If the
SCSI reset signal goes true when this bit is set, the FSC
disconnects from the SCSI bus and remains idle in the
disconnected state without interrupting the host. If the bit
is not set, the FSC responds to the SCSI reset by first
interrupting the host. This bit is cleared by hardware reset
or the Chip Reset command, but not SCSI reset.
Parity Test Mode
With this bit set, the parity bit equals bit 7 when unloading
the FIFO to the SCSI bus and using a DMA command.
For non-DMA commands, standard odd parity is
generated on the SCSI bus. This allows parity errors to
be created so that hardware and software may be tested.
This bit must not be set during normal operation. Refer
to
page
Chip Reset command, but not SCSI reset.
Section 2.3, “Parity Checking and Generation,”
PTest
2-6. This bit is cleared by hardware reset or the
5
0
PChk
4
0
Default
CTEST
3
0
2
0
MBID
0
on
0
0
7
6
5