LSI53CF92A LSI, LSI53CF92A Datasheet - Page 78

• Manufacturer Part Number: LSI53CF92A
• Manufacturer: LSI

Specifications of LSI53CF92A

• Lead Free Status / RoHS Status: Not Compliant

4-28
Register: 0x0B
Configuration 2 (Config 2)
Read/Write
Register Bank 0
After hardware reset or the Reset command, the bits in this register are
all cleared, which makes the chip compatible with LSI53C90 family
software. Any bit pattern written to this register may be read back and
should be identical. The default value of this register is 0x20.
R
FE
R
DHZ
Registers
Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved.
R
7
0
FE
6
0
Reserved
This bit must be set to 0.
Features Enable
This bit is cleared by hardware reset or the software
Reset command, and is not affected by SCSI reset.
When set, this bit enables all of the following features:
Reserved
This bit must be set to 0.
DREQ High Impedance
When this bit is set, the DREQ output (DMA request)
goes to high impedance and does not significantly load a
TTL-compatible device. This is useful when several
The SCSI phase is latched at each command
completion. This permits simpler software routines for
stacked commands. When this bit is not set, the
phase bits reported in the
indicators of the state of the SCSI phase lines.
The
enabled, which extends the transfer counter from 16
to 24 bits. If other conditions are met, setting this bit
also allows the chip revision code to be read (see the
Transfer Counter High/ID
information on this feature).
R
5
0
Transfer Counter High/ID
DHZ
4
0
Default
SCSI2
3
0
register description for more
Status
BPA
(0x0E) register is
2
0
register are live
R
1
0
DPE
0
0
7
6
5
4