LSI53CF92A LSI, LSI53CF92A Datasheet - Page 32

• Manufacturer Part Number: LSI53CF92A
• Manufacturer: LSI

Specifications of LSI53CF92A

• Lead Free Status / RoHS Status: Not Compliant

2.5.4.1 Deassertion of DREQ
2.5.4.2 DMA Read
2-12
In the Multiplexed Bus Configuration mode, the FSC is designed to
operate with a DMA controller that has timings similar to an 8237.
Because many systems use one of the 8237 channels for DRAM refresh
and because the 8237 does not recognize a higher priority request until
it finishes its current transfer, Burst mode gives the best transfer rate
without sacrificing memory integrity.
The FSC remains in Burst mode as long as more than eight bytes remain
to be transferred. However, if the Transfer Counter drops below eight,
then the FSC switches out of Burst mode for the last one to seven bytes.
The last bytes are transferred in Normal DMA mode where DREQ goes
true and stays true as long as the FIFO is able to transfer data; DACK/
cycles true then false for each transfer. Because DACK/ must cycle true
then false for every DMA transfer in this mode, Normal mode is
sometimes referred to as Single Transfer mode.
When DMA Burst mode is enabled, the method by which DMA read data
is transferred to the system bus depends on the bus configuration mode.
The DMA read data is enabled onto the DB bus by DACK/ and either the
RD/ or DBRD/ input signal, as follows.
Functional Description
Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved.
Single Transfer Mode: DREQ goes true and stays true as long as
the FIFO is able to transfer data. DACK/ cycles true then false for
every transfer.
Multiple DMA Transfers per DREQ: In the Multiplexed Bus
Configuration mode, DREQ is deasserted after the trailing edge of
DBWR/ or DBRD/. DACK/ remains asserted throughout multiple
transfers. In the Nonmultiplexed Bus Configuration mode, DREQ is
deasserted after the trailing edge of DACK/ of the next-to-last DMA
transfer. In the Nonmultiplexed Bus Configuration mode, DACK/
toggles for each DMA read cycle.