LSI53CF92A LSI, LSI53CF92A Datasheet - Page 77

• Manufacturer Part Number: LSI53CF92A
• Manufacturer: LSI

Specifications of LSI53CF92A

• Lead Free Status / RoHS Status: Not Compliant

Register: 0x0A
Test
Write Only
Register Bank 0
This register is enabled by setting the special test mode bit in
Configuration 1 (Config 1)
been entered, a hardware reset or the Reset command must occur
before normal operation can begin. These bits must not be set during
normal chip operation.
R
R
HIGH-Z
Init
Tar
Standard Register Set
Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved.
7
0
0
Reserved
Reserved
These bits must be set to 0.
All Outputs to High Impedance
When this bit is set, all bidirectional and all output pins
go to high impedance and do not significantly load a TTL
or compatible device.
Initiator Mode
When this bit is set, the FSC is artificially forced into initiator
mode. Any initiator command is accepted by the FSC. For
example, a Set ATN command causes ATN/ to be driven on
the SCSI bus even if the FSC is disconnected.
Target Mode
When this bit is set, the FSC is artificially forced into
target mode. Any target command is accepted by the
FSC. For example, a DMA command loads or unloads the
FIFO and sets the SCSI phase, Data, and REQ/ signals
even if arbitration and selection have not occurred.
R
0
register at address 0x08. After test mode has
0
Default
3
0
HIGH-Z
2
0
Init
1
0
Tar
0
0
[7:5]
[4:3]
4-27
2
1
0