LSI53CF92A LSI, LSI53CF92A Datasheet - Page 71

• Manufacturer Part Number: LSI53CF92A
• Manufacturer: LSI

Specifications of LSI53CF92A

• Lead Free Status / RoHS Status: Not Compliant

Register: 0x07
FIFO Flags
Read Only
Register Bank 0 or 1
The least significant five bits of this register indicate how many bytes are
currently in the FIFO. The value is binary encoded. The flags should not
be polled while transferring data because they are not stable while the
SCSI interface is changing the contents of the FIFO.
The upper three bits are duplicates of the
normal mode. If Test Mode is enabled, bit 5 is set to indicate that the
offset counter is not zero. Not zero means that synchronous data may
continue to be transferred. Zero means that the synchronous offset count
has expired, and the FSC does not transfer any more data until it
receives an acknowledge.
Register: 0x07
Synchronous Offset
Write Only
Register Bank 0 or 1
Bits [7:6] of this register control when the REQ/ and ACK/ signals
deassert by selecting one of four input clock edges. These bits only affect
a Synchronous Data In or Synchronous Data Out phase. The control over
deassertion of these signals is measured in input clock cycles and is
dependent on the status of the FASTCLK bit,
bit 3, as shown in
Standard Register Set
Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved.
Deassertion Delay
SS2
7
0
7
0
SS1
6
0
6
0
Table
SS0
Assertion Delay
5
0
5
0
4.5.
FF4
4
0
4
0
Default
FF3
3
0
3
0
Sequence Step
Synchronous/Asynchronous
Configuration 3 (Config
FF2
2
0
2
0
FF1
register bits in
1
0
1
0
FF0
0
0
0
0
4-21
3),