LSI53CF92A LSI, LSI53CF92A Datasheet - Page 153

• Manufacturer Part Number: LSI53CF92A
• Manufacturer: LSI

Specifications of LSI53CF92A

• Lead Free Status / RoHS Status: Not Compliant

register reset values, table
register set, table
registers
reset levels
SCSI output control latch (SOCL) register
SCSI output data latch (SODL) register
SCSI status (SSTATUS) register
sequence step register
status register
test register
transfer counter high/ID register
SCAM registers
standard registers
synchronous offset
disconnect reset
hard reset
soft reset
low level parity control bit
time-out test bit
assert SCSI ACK/ bit
assert SCSI ATN/ bit
assert SCSI BSY/ bit
assert SCSI C/D/ bit
assert SCSI I/O/ bit
assert SCSI MSG/ bit
assert SCSI REQ/ bit
assert SCSI SEL/ bit
bits SD[7:0]
arbitration delay1 bit
arbitration delay4 bit
SCSI parity status bit
SCSI reset status bit
sequence step bits
synchronous offset max bit
parity error bit
terminal count bit
valid group code bit
all outputs to high impedance bit
initiator mode bit
target mode bit
chip family ID bits
chip revision level bits
SCSI bus control lines (SBCL)
SCSI bus data lines (SBDL)
SCSI control (SCONTROL)
SCSI output control latch (SOCL)
SCSI output data latch (SODL)
SCSI status (SSTATUS)
clock conversion
command
configuration 1
configuration 2
configuration 3
configuration 4
destination bus ID
FIFO
FIFO flags
interrupt
sequence step
status
synchronous transfer period
test
time-out
transfer counter 4-4,
transfer counter high/ID
4-27
4-7
2-16
4-10
2-15
4-14
4-16
4-3
4-8
4-21
4-42
2-17
4-11
4-17
4-24
4-28
4-30
4-34
4-21
4-27
4-37
4-27
4-26
4-11
4-36
4-13
4-17
4-2
4-40
4-12
Index
Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved.
4-40
4-39
4-39
4-5
4-40
4-39
4-40
4-40
4-40
4-40
4-39
4-40
4-36
4-35
4-39
4-37
4-17
4-37
4-18
4-42
4-41
4-42
4-27
4-40
S
SCAM
SCAM register set
SCSI bus control lines (SBCL) register
SCSI bus data lines (SBDL) register
SCSI configured automatically (SCAM) capability
SCSI control (SCONTROL) register
SCSI data transfer rates
SCSI operation
SCSI output control latch (SOCL) register
SCSI output data latch (SODL) register
SCSI status (SSTATUS) register
SCSI timings
sequence step register
single-pin, single-ended SCSI
soft reset
standard register set
status register
synchronous offset register
synchronous operation
synchronous transfer period register
T
test register
threshold eight mode
SCSI ACK/ asserted bit
SCSI ATN/ asserted bit
SCSI BSY/ asserted bit
SCSI C/D/ asserted bit
SCSI I/O/ asserted bit
SCSI MSG/ asserted bit
SCSI REQ/ asserted bit
SCSI SEL/ asserted bit
bits SD[7:0]
arbitrate bit
assert data bus bit
enable delayed response to selection bit
enable SCAM selection response bit
low level bit
low level parity control bit
time-out test bit
asynchronous operation
synchronous operation
assert SCSI ACK/ bit
assert SCSI ATN/ bit
assert SCSI BSY/ bit
assert SCSI C/D/ bit
assert SCSI I/O/ bit
assert SCSI MSG/ bit
assert SCSI REQ/ bit
assert SCSI SEL/ bit
bits SD[7:0]
arbitration delay1 bit
arbitration delay4 bit
SCSI parity status bit
SCSI reset status bit
sequence step bits
synchronous offset max bit
parity error bit
terminal count bit
valid group code bit
all outputs to high impedance bit
initiator mode bit
target mode bit
4-36
2-16
4-27
6-23
4-10
4-38
2-2
4-42
4-42
4-38
4-11
4-36
4-27
4-37
4-27
4-4
4-11
2-10
4-38
4-17
2-14
4-17
4-40
4-12
4-40
4-39
4-39
4-40
4-39
4-40
4-40
4-40
4-40
4-39
4-40
4-41
2-14
4-41
4-41
4-21
4-41
4-41
4-41
4-41
2-14
4-41
4-37
2-13
4-17
4-39
4-37
4-18
4-42
4-27
4-41
4-42
4-38
4-40
4-37
1-2
IX-3