LSI53CF92A LSI, LSI53CF92A Datasheet - Page 54

• Manufacturer Part Number: LSI53CF92A
• Manufacturer: LSI

Specifications of LSI53CF92A

• Lead Free Status / RoHS Status: Not Compliant

4.1 Standard Register Set
4-4
The Standard Register Set can be accessed when CS/ is true. The
specific register being accessed is determined by the states of the RD/
and WR/ signals together with the address pins A[3:0]. The state of
bit 3 of
registers. Registers 0x00 through 0x07 of the Standard Register Set are
accessible with either register bank setting. Registers 0x08 through 0x0F
of the Standard Register Set are accessible when bank 0 is selected,
and the SCAM Register Set is accessible in registers 0x08 through 0x0F
when register bank 1 is selected. The complete register map, including
SCAM registers, is shown in
Register: 0x00–0x01
Transfer Counter
Write Only
Register Bank 0 or 1
These two registers, together with the
(0x0E), form a 24-bit register which stores the Transfer Count value for
DMA operations. They specify the number of bytes that are to be
transferred over the SCSI bus. Values written to these two registers are
stored internally and loaded into the transfer count by any DMA
command. These values remain unchanged while the transfer counter
decrements. Thus, successive blocks of equal size may be transferred
without reprogramming the count. They may be reprogrammed any time
after the previous DMA operation has started, whether it has finished or
not. When the Features Enable bit is clear (which disables the
Transfer Counter High/ID
specifies a maximum length count of 64 Kbytes. When the Features
Enable bit is set, and the
zeros specify a maximum length count of 16 Mbytes. These registers are
not changed by any reset. Their states are unpredictable after power-up.
Registers
Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved.
7
x
Configuration 4 (Config 4)
6
x
5
x
register), a zero value in registers 00 and 01
Transfer Counter High/ID
Table 4.2
4
x
Default
selects between two banks of
Transfer Counter High/ID
on page 4-3.
3
x
2
x
register is enabled,
1
x
register
0
x