IPSERIALLITE Altera, IPSERIALLITE Datasheet - Page 105

• Manufacturer Part Number: IPSERIALLITE
• Manufacturer: Altera

Specifications of IPSERIALLITE

• Lead Free Status / RoHS Status: Not Compliant

General
Description
Testbench
Environment
Altera Corporation
August 2005
f
You can simulate your design using IP Toolbench-generated VHDL and
Verilog HDL IP functional simulation models.
For more information on IP functional simulation models, see the
Simulating Altera in Third-Party Simulation Tools chapter in Volume 3 of
the Quartus II Handbook.
Altera provides models you can use for functional verification of the
SerialLite MegaCore
demonstration testbench, including scripts to run it, is also provided. This
demonstration testbench, used with the ModelSim
tool, demonstrates how to instantiate a model in a design. The
demonstration testbench stimulates the inputs and checks the outputs of
the interfaces of the SerialLite MegaCore function, demonstrating basic
functionality.
The testbench (seriallite_tb) environment shown in
generates traffic through the Atlantic
it through the SerialLite logic, loops the data back on the high-speed serial
interface, back into the receive side of the logic, and then checks the data
as received at the Atlantic interface (atl_mon). The SerialLite status bus
is monitored throughout the duration of the testbench by the status
monitor (stat_mon).
MegaCore Function Version 1.1.0
®
function within your design. A Verilog HDL
4. SerialLite Testbench
™
port generators (atl_gen), sends
®
-Altera simulator
Figure 4–1
Preliminary
4–1