IPSERIALLITE Altera, IPSERIALLITE Datasheet - Page 47

• Manufacturer Part Number: IPSERIALLITE
• Manufacturer: Altera

Specifications of IPSERIALLITE

• Lead Free Status / RoHS Status: Not Compliant

Specifications
Altera Corporation
August 2005
Aggregate Bandwidth
The bit rate specifies the rate of data transmission on a single lane. In a
multi-lane configuration, the total available bandwidth is the single-lane
bit rate multiplied by the number of lanes.
Effective Data Rate
The bit rate sets the rate at which bits are sent across the high-speed serial
link. This is not equivalent to the effective data rate. For example, because
8B/10B encoding is used, each 10 bits of transmitted data corresponds to
only 8 bits of actual data.
The effective data rate can also be further reduced by other features such
as clock compensation, use of the priority port, and the retry-on-error
feature. These and other features affect the data rate because they use the
same link to transmit various control packets or priority packets in the
middle of data packets. While the effect of these features should not be
ignored, it may be very small.
The data rate can be further reduced by an inefficient implementation. In
particular, using small packets on a link with many lanes, or setting the
FIFO buffer sizes and flow control pauses such that the link spends too
much time pausing are examples of implementations that reduce the data
bandwidth. In these cases, you can improve bandwidth by making
adjustments to improve efficiency. Altera provides a Microsoft
Excel-based tool that can help you estimate and improve the efficiency of
your SerialLite link. You can find the calculator and Application Note 389:
SerialLite MegaCore Function Bandwidth Calculator at
www.altera.com/products/ip/communications/additional_functions_
comm/m-alt-seriallite.html.
The relationships between the various rates are illustrated in
on page
MegaCore Function Version 1.1.0
3–16.
SerialLite MegaCore Function User Guide
Figure 3–10
3–15