IPSERIALLITE Altera, IPSERIALLITE Datasheet - Page 40

• Manufacturer Part Number: IPSERIALLITE
• Manufacturer: Altera

Specifications of IPSERIALLITE

• Lead Free Status / RoHS Status: Not Compliant

SerialLite Link Configuration
3–8
SerialLite MegaCore Function User Guide
TDAT[]
THDAT[]
RDAT[]
RHDAT[]
TADR[]
THADR[]
RADR[]
RHADR[]
Table 3–2. Atlantic Interface Signals (Part 1 of 4)
Name
Input
Output
Input
Output
Direction
Data buses. A data bus carries the main payload data. The width of the bus is
determined by the number of lanes in the SerialLite MegaCore function
configuration. The width, in bytes, is twice the number of lanes. For example, a
1-lane configuration is 2 bytes wide and a 4-lane configuration is 8 bytes wide. The
system logic places data on the data bus for transmission, and reads data on the
data bus for reception.
Data is presented in big-endian order. Valid bytes are aligned with the most
significant byte (MSB). For example, in a 2-lane configuration (which has a
4-byte-wide data bus), if only 3 bytes are valid on the final cycle of a packet, the valid
data appears on bits
of the data bus.
TDAT[]
THDAT[]
RDAT[]
the regular data port.
RHDAT[]
the priority data port.
The optional address buses. An address bus is only used on ports that enable
Channel Multiplexing. The system logic places the channel number on the address
bus for transmission, and reads the channel number from the address bus on
reception. The width of the address bus is determined by the number of channels
being multiplexed. The address bus must be valid at the same time as the data bus,
and must remain constant throughout a complete packet.
TADR[]
data port if channel multiplexing is enabled for the regular data port.
THADR[]
data port if channel multiplexing is enabled for the priority data port.
RADR[]
channel number on the regular data port if channel multiplexing is enabled for the
regular data port.
RHADR[]
channel number on the priority data port if channel multiplexing is enabled for the
priority data port.
The Atlantic interface signals are described in
required for a given configuration, as well as the appropriate bus widths,
are created automatically by IP Toolbench based upon the features you
select. All Atlantic interface signals operate in the system clock domain.
is driven by the system logic to transmit the channel number on the regular
is driven by the system logic to transmit data on the regular data port.
is driven by the SerialLite MegaCore function to deliver received data on
is driven by the SerialLite MegaCore function to deliver the received
MegaCore Function Version 1.1.0
is driven by the system logic to transmit the channel number on the priority
is driven by the system logic to transmit data on the priority data port.
is driven by the SerialLite MegaCore function to deliver received data on
is driven by the SerialLite MegaCore function to deliver the received
[31..8]
of the data bus, and the invalid byte is bits
Description
Table
3–2. The signals
Altera Corporation
August 2005
[7..0]