IPSERIALLITE Altera, IPSERIALLITE Datasheet - Page 48

• Manufacturer Part Number: IPSERIALLITE
• Manufacturer: Altera

Specifications of IPSERIALLITE

• Lead Free Status / RoHS Status: Not Compliant

SerialLite Link Configuration
Figure 3–10. Clock Relationships
3–16
SerialLite MegaCore Function User Guide
System
Logic
Effective Data Rate
(Less Than Bit Rate)
System Clock Rate
(= 1/20 Bit Rate)
Scaling by Adding Lanes
Because each lane operates at the bit rate, you can increase bandwidth by
adding lanes. This is a simple way to scale the link during system design.
If adding a lane provides more bandwidth than needed, you can reduce
the system clock rate, mitigating possible high-speed design issues and
making it easier to meet performance. By setting an appropriate clock rate
and lane width, a desired aggregate bit rate can be achieved. The
aggregate bandwidth is reported in the Parameterize - SerialLite
MegaCore function wizard, as shown in
Figure 3–11. Aggregate Bit Rate
MegaCore Function Version 1.1.0
Atlantic Interface
MegaCore
SerialLite
Function
(x20)
PLL
High-Speed
Serial Interface
Figure
(= 20 X System Clock Rate)
3–11.
Bit Rate
Altera Corporation
August 2005