IPSERIALLITE Altera, IPSERIALLITE Datasheet - Page 51

• Manufacturer Part Number: IPSERIALLITE
• Manufacturer: Altera

Specifications of IPSERIALLITE

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Specifications
Altera Corporation
August 2005
Summary of Bandwidth-Related Settings
Table 3–9
of the SerialLite link.
Clock Compensation
The configuration of your system clock or clocks determines whether or
not you need to use clock compensation.
Clock Domains
The SerialLite internal logic contains two clock domains. The majority of
the logic is clocked by the system clock via the CLK signal. However, a
small part of the receiver logic is clocked by the clock signal recovered
from the received data stream. The received data has to cross from this
recovered clock domain into the system clock domain, as illustrated in
Figure
one domain to the other. Depending on the relationship between the
system clock and the recovered clock, compensation may be required to
ensure that no data is lost due to a frequency mismatch.
Bit rate
Automatically
adjust for best
simulation
Lane count
Signal
propagation
delay
Table 3–9. Bandwidth-Related Settings
Setting
MegaCore Function Version 1.1.0
3–13. A FIFO memory is used to buffer the data as it crosses from
summarizes the different ways you can change the bandwidth
Specifies the rate at which bits are sent on the high-speed
serial interface. Equal to 20× the system clock rate, and faster
than the effective data rate.
Used to ensure that the bit rate chosen corresponds to a
picosecond-integer system clock period.
The number of lanes to be created. Each lane operates at the
specified bit rate.
The propagation delay of a signal from when it is placed on the
TX_OUT
RX_IN
pins of the other end of the link.
pins of one end of the link to when it is received on the
SerialLite MegaCore Function User Guide
Description
3–19