ACS8525AT Semtech, ACS8525AT Datasheet - Page 11

• Manufacturer Part Number: ACS8525AT
• Manufacturer: Semtech

Specifications of ACS8525AT

• Lead Free Status / RoHS Status: Compliant

Disqualification of a non-selected SEC is based on
inactivity noted by the Activity Monitors. The currently
selected SEC can be disqualified for being out-of phase,
inactive, or if the source is outside the DPLL lock range.
If the currently selected SEC is disqualified, the next
highest priority qualified SEC is selected.
Interrupts for Activity Monitors
The loss of the currently selected SEC will eventually
cause the input to be considered invalid, triggering an
interrupt. The time taken to raise this interrupt is
dependant on the Leaky Bucket Configuration of the
activity monitors. The fastest Leaky Bucket setting will still
take up to 128 ms to trigger the interrupt. The interrupt
caused by the brief loss of the currently selected SEC is
provided to facilitate very fast source failure detection if
desired. It is triggered after missing just a couple of cycles
of the SEC. Some applications require the facility to switch
downstream devices based on the status of the SECs. In
order to provide extra flexibility, it is possible to flag the
main_ref_failed interrupt (Reg. 06 Bit 6) on the pin TDO.
This is simply a copy of the status bit in the interrupt
register and is independent of the mask register settings.
The bit is reset by writing to the interrupt status register in
the normal way. This feature can be enabled and disabled
by writing to Reg. 48 Bit 6.
Leaky Bucket Timing
The time taken (in seconds) to raise an inactivity alarm on
an SEC that has previously been fully active (Leaky Bucket
empty) will be:
where n is the number of the Leaky Bucket Configuration.
If an input is intermittently inactive then this time can be
longer. The default setting of cnfg_upper_threshold_n is
6, therefore the default time is 0.75 s.
The time taken (in seconds) to cancel the activity alarm on
a previously completely inactive SEC is calculated, for a
particular Leaky Bucket, as:
where:
Revision 1.00/September 2007 © Semtech Corp.
ADVANCED COMMS & SENSING
(cnfg_upper_threshold_n) / 8
[2
a = cnfg_decay_rate_n
b = cnfg_Bucket_size_n
c = cnfg_lower_threshold_n
(where n = the number of the relevant Leaky
Bucket Configuration in each case).
(a)
x (b - c)]/ 8
FINAL
Page 11
The default setting is shown in the following:
Fast Activity Monitor
Anomalies on the selected clock have to be detected as
they occur and the PLL must be temporarily isolated until
the clock is once again pure. The SEC activity monitoring
process cannot be used for this because the high degree
of accuracy required dictates that the process be slow. To
achieve the immediacy required, the PLL requires an
alternative mechanism. The phase locked loop itself
contains a fast activity detector such that within
approximately two missing input clock cycles, a no-activity
flag is raised and the DPLL is frozen in Digital Holdover
mode. This flag can also be read as the DPLL1
main_ref_failed bit (from Reg. 06 sts_interrupts, Bit 6)
and can be set to indicate a phase lost state by enabling
Reg. 73, Bit 6. With the DPLL in Digital Holdover mode it
is isolated from further disturbances. If the input becomes
available again before the activity monitor rejection alarm
has been raised, then the DPLL will continue to lock to the
input, with little disturbance. In this scenario, with the
DPLL in the “locked” state, the DPLL uses “nearest edge
locking” mode (±180° capture) avoiding cycle slips or
glitches caused by trying to lock to an edge 360° away, as
would happen with traditional PLLs.
Selector
This block has two main functions:
Selection of Input SECs
Under normal operation, the input SECs are selected
automatically by an order of priority given in the Priority
Table. For special circumstances however, such as chip or
board testing, the selection may be forced by
configuration.
Automatic operation selects an SEC based on its
predefined priority and its current validity. A table is
maintained which lists all valid SECs in the order of
priority. This is initially downloaded into the ACS8525A via
the Serial interface by the Network Manager, and is
subsequently modified by the results of the ongoing
quality monitoring. In this way, when all the defined
Selection of the Input reference clock source via
Reg. 33 force_select_reference_source
Forcing of the Operating mode of the device, via
Reg. 32 cnfg_operating_mode
[2
1
x (8 - 4)] /8 = 1.0 secs
ACS8525A LC/P
DATASHEET
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