ACS8525AT Semtech, ACS8525AT Datasheet - Page 35

• Manufacturer Part Number: ACS8525AT
• Manufacturer: Semtech

Specifications of ACS8525AT

• Lead Free Status / RoHS Status: Compliant

either 19.44 MHz (when the current locked to reference is
19.44 MHz) or 38.88 MHz (all other frequencies). This
would allow, for instance, a 19.44 MHz and 2 kHz pair to
be used for Line Card synchronization.
Reg. 7B Bit 7, Indep_FrSync/MFrSync controls whether
the 2 kHz MFrSync and 8 kHz FrSync outputs keep their
precise alignment with the other output clocks. When
Indep_FrSync/MFrSync Reg. 7B Bit 7 is Low the FrSyncs
and the other higher rate clocks are not independent and
their alignment on the falling 8kHz edge is maintained.
This means that when bit Sync_OC-N_rates is High, the
OC-N rate dividers and clocks are also synchronized by the
Sync input. On a change of phase position of the Sync, this
could result in a shift in phase of the 6.48 MHz output
clock when a 19.44 MHz precision is used for the Sync
input. To avoid disturbing any of the output clocks and
only align the MFrSync and FrSync outputs, at the chosen
level of precision, Independent Frame Sync mode can be
used (Reg. 7B, Bit 7 = 1). Edge alignment of the FrSync
output with other clocks outputs may then change
depending on the selected Sync sampling precision used.
For example with a 19.44 MHz reference input clock and
Reg. 7B Bits 6 & 7 both High (independent mode and
Sync OC-N rates), then the FrSync output will still align
with the 19.44 MHz output but not with the 6.48 MHz
output clock.
The FrSync and MFrSync outputs always come from
DPLL1. 2 kHz and 8 kHz outputs can also be produced at
the O1 to O2 outputs. These can come from either the
DPLL1 or from the DPLL2, controlled by Reg. 7A, Bit 7.
Revision 1.00/September 2007 © Semtech Corp.
ADVANCED COMMS & SENSING
FINAL
Page 35
Power-On Reset
The Power-On Reset (PORB) pin resets the device if forced
Low. The reset is asynchronous, the minimum Low pulse
width is 5 ns. Reset is needed to initialize all of the
register values to their defaults. Reset must be asserted
at power on, and may be re-asserted at any time to restore
defaults. This is implemented simply using an external
capacitor to GND along with the internal pull-up resistor.
The ACS8525A is held in a reset state for 250 ms after the
PORB pin has been pulled High. In normal operation PORB
should be held High.
Serial Interface
The ACS8525A device has a serial interface which can be
SPI compatible. The Motorola SPI Convention is such that
address and data is transmitted and received MSB first.
On the ACS8525A address and data are transmitted and
received LSB first. Address, read/write control and data
on the SDI pin are latched into the device on the rising
edge of the SCLK. During a read operation, serial data
output on the SDO pin can be read out of the device on
either the rising or falling edge of the SCLK depending on
the logic level of CLKE. For standard Motorola SPI
compliance, data should be clocked out of the SDO pin on
the rising edge of the SCLK so that it may be latched into
the microprocessor on the falling edge of the SCLK.
Figure 10 and Figure 11 show the timing diagrams of
read and write accesses for this interface.
The serial interface clock (SCLK) is not required to run
between accesses (i.e., when CSB = 1).
ACS8525A LC/P
DATASHEET
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