ACS8525AT Semtech, ACS8525AT Datasheet - Page 2

• Manufacturer Part Number: ACS8525AT
• Manufacturer: Semtech

Specifications of ACS8525AT

• Lead Free Status / RoHS Status: Compliant

Section
Description ................................................................................................................................................................................................. 1
Block Diagram ............................................................................................................................................................................................1
Features .....................................................................................................................................................................................................1
Pin Diagram ...............................................................................................................................................................................................4
Pin Description ...........................................................................................................................................................................................5
Introduction ................................................................................................................................................................................................6
General Description ...................................................................................................................................................................................7
Register Map ........................................................................................................................................................................................... 38
Register Descriptions ............................................................................................................................................................................. 42
Revision 1.00/September 2007 © Semtech Corp.
ADVANCED COMMS & SENSING
Table of Contents
Inputs .................................................................................................................................................................................................7
Input SEC Activity Monitors ..............................................................................................................................................................9
Selector ........................................................................................................................................................................................... 11
Phase Locked Loops (PLLs) .......................................................................................................................................................... 13
Outputs ........................................................................................................................................................................................... 22
Operating Modes (States) of the Device ...................................................................................................................................... 30
Local Oscillator Clock ..................................................................................................................................................................... 32
Status Reporting and Phase Measurement ................................................................................................................................. 32
Sync Reference Sources ............................................................................................................................................................... 33
Power-On Reset .............................................................................................................................................................................. 35
Serial Interface ............................................................................................................................................................................... 35
Register Organization .................................................................................................................................................................... 38
Preconfiguring Inputs ...............................................................................................................................................................8
PECL/LVDS Input Port Selection .............................................................................................................................................9
Input Locking Frequency Modes .............................................................................................................................................9
Leaky Bucket Accumulator ................................................................................................................................................... 10
Fast Activity Monitor .............................................................................................................................................................. 11
Selection of Input SECs ......................................................................................................................................................... 11
External Protection Switching Mode-SRCSW pin ................................................................................................................ 13
Output Clock Phase Continuity on Source Switchover ....................................................................................................... 13
Forcing of the Operating Mode of the Device ...................................................................................................................... 13
PLL Overview ......................................................................................................................................................................... 13
PLL Architecture .................................................................................................................................................................... 14
PLL Operational Controls ...................................................................................................................................................... 17
Phase Compensation Functions .......................................................................................................................................... 19
DPLL Feature Summary ........................................................................................................................................................ 20
PECL/LVDS Output Port Selection ....................................................................................................................................... 22
Output Frequency Selection and PLL Configuration ........................................................................................................... 22
Free-run Mode ....................................................................................................................................................................... 30
Pre-locked Mode ................................................................................................................................................................... 30
Locked Mode ......................................................................................................................................................................... 30
Lost-phase Mode ................................................................................................................................................................... 30
Digital Holdover Mode ........................................................................................................................................................... 30
Pre-locked2 Mode ................................................................................................................................................................. 32
Input Status Interrupts .......................................................................................................................................................... 32
Input Status Information ....................................................................................................................................................... 32
DPLL Frequency Reporting ................................................................................................................................................... 32
Measuring Phase Between Master and Slave/Stand-by SEC Sources ............................................................................. 33
Aligning Phase of MFrSync and FrSync Outputs to Phase of Sync Inputs ......................................................................... 34
Multi-word Registers ............................................................................................................................................................. 38
Register Access ..................................................................................................................................................................... 38
Interrupt Enable and Clear ................................................................................................................................................... 38
Defaults .................................................................................................................................................................................. 38
FINAL
Page 2
ACS8525A LC/P
DATASHEET
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