ACS8525AT Semtech, ACS8525AT Datasheet - Page 91

• Manufacturer Part Number: ACS8525AT
• Manufacturer: Semtech

Specifications of ACS8525AT

• Lead Free Status / RoHS Status: Compliant

Address (hex):
Address (hex):
Revision 1.00/September 2007 © Semtech Corp.
ADVANCED COMMS & SENSING
Register Name
coarse_lim_
phaseloss_en
Register Name
ip_noise_
window_en
Bit No.
Bit No.
Bit 7
[3:0]
Bit 7
[6:0]
7
74 (cont...)
76
cnfg_phase_loss_coarse_limit
wide_range_en multi_ph_resp
Description
phase_loss_coarse_limit
Sets the range of the coarse phase loss detector
and the coarse phase detector.
When locking to a high frequency signal, and jitter
tolerance greater than 0.5 UI is required, then the
DPLL can be configured to track phase errors over
many input clock periods. This is particularly useful
with very low bandwidths. This register configures
how many UI over which the input phase can be
tracked. It also sets the range of the coarse phase
loss detector, which can be used with or without the
multi-UI phase capture range capability.
This register value is used by Bits 6 and 7.
cnfg_ip_noise_window
Description
ip_noise_window_en
Register bit to enable a window of 5% tolerance
around low-frequency inputs (2, 4 and 8 kHz). This
feature ensures that any edge caused by noise
outside the 5% window where the edge is expected
will not be considered within the DPLL. This reduces
any possible phase hit when a low-frequency
connection is removed and contact bounce is
possible.
Not used.
Bit 6
Bit 6
Bit 5
Bit 5
Description
Description
Bit 4
Bit 4
FINAL
Page 91
(R/W) Register to configure some
of the parameters of DPLL phase
detectors.
(R/W) Register to configure the
noise rejection function for low
frequency inputs.
1100-1111
Bit Value
Bit Value
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
Bit 3
Bit 3
0
1
-
Value Description
Input phase error tracked over ±1 UI.
Input phase error tracked over ±3 UI.
Input phase error tracked over ±7 UI.
Input phase error tracked over ±15 UI.
Input phase error tracked over ±31 UI.
Input phase error tracked over ±63 UI.
Input phase error tracked over ±127 UI.
Input phase error tracked over ±255 UI.
Input phase error tracked over ±511 UI.
Input phase error tracked over ±1023 UI.
Input phase error tracked over ±2047 UI.
Input phase error tracked over ±4095 UI.
Input phase error tracked over ±8191 UI.
Value Description
DPLL considers all edges for phase locking.
DPLL ignores input edges outside a 95% to 105%
window.
-
phase_loss_coarse_limit
Bit 2
Bit 2
ACS8525A LC/P
Default Value
Default Value
Bit 1
Bit 1
DATASHEET
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1000 0101
0000 0110
Bit 0
Bit 0