ACS8525AT Semtech, ACS8525AT Datasheet - Page 17

• Manufacturer Part Number: ACS8525AT
• Manufacturer: Semtech

Specifications of ACS8525AT

• Lead Free Status / RoHS Status: Compliant

APLLs
There are three main APLLs. APLL1 and APLL2 provide a
lower final output jitter reducing the 4.9 ns p-p jitter from
the digital down to 500 ps p-p and 60 ps rms as typical
final outputs measured broadband (from 10 Hz to 1 GHz).
The feedback APLL (APLL3) is selected by default; it
provides improved performance over the digital feedback.
APLL Output Dividers
Each APLL has its own divider. Each divider
simultaneously outputs a series of fixed ratios of its APLL
input. Any of these divided outputs may be selected as the
output on Output Ports O1 or O2 by configuring Reg. 61
and Reg. 62, with the following exceptions: (APLL1)/2 and
(APLL1)/1 only available for Output 01 (differential port),
and (APLL1)/48 only available for Output 02.
PFD and Loop Filters
The PFD compares the input reference with that of the
locking frequency (feedback) giving a phase error which is
then filtered by a 100 Hz low pass filter, to give the
average phase error for input into a loop filter. The PFD is
quite complex and has several programmable options to
determine what phase error value is fed to the loop (see
“Phase and Frequency Detectors” on page 18) depending
on the type of jitter/wander expected.
The loop filter bandwidth and damping is programmable
to optimize the locking time/ability to track the input. See
“Damping Factor Programmability” on page 18 and
Figure 6 on page 18.
PLL Operational Controls
The main factors controlling the operation of the PLL are:
1. The operating mode of the device. See “Operating
2. Input reference and feedback frequency selection.
3. Loop Bandwidth (Input Acquisition/Locked
4. PFD settings - these affect the input phase error to the
Revision 1.00/September 2007 © Semtech Corp.
ADVANCED COMMS & SENSING
Modes (States) of the Device” on page 30.
See “PLL Architecture” on page 14 and “Input Locking
Frequency Modes” on page 9.
Bandwidth) and Damping factor of the DPLLs - these
determine how fast the device can to lock to the
selected input, or how tightly it can track the input.
See from “Input Acquisition Bandwidth” to “Damping
Factor Programmability” next.
Loop filter and relate to jitter and wander tolerance.
See “Phase/Frequency/Lock Detection” on page 18.
FINAL
Page 17
5. Phase compensation functions - See “Phase
Input Acquisition Bandwidth
DPLL1 has programmable acquisition bandwidth of 18,
35 or 70 Hz. The default is set to 70 Hz.
Input Locked Bandwidth
The ACS8525A has programmable Locked Bandwidth of
18, 35 or 70 Hz. These bandwidth settings correspond to
the -3 dB jitter attenuation point on the ACS8525A’s jitter
transfer characteristic shown in Figure 6. If the
ACS8525A is used with only DPLL1, the highest
bandwidth setting is recommended to ensure the closest
tracking of the input SEC. If DPLL2 is also to be used,
DPLL1 should be set to a lower bandwidth setting than
DPLL2. The lowest bandwidth setting will provide the
highest jitter attenuation although this is not the main
function of the ACS8525A device.
Table 5 Available Damping Factors for different DPLL
Bandwidths, and Associated Gain Peak Values
18
35
70
Bandwidth/Hz
Compensation Functions” on page 19.
1
2
3, 4, 5
1
2
3
4, 5
1
2
3
4
5
Reg. 6B [2:0]
ACS8525A LC/P
1.2
2.5
5
1.2
2.5
5
10
1.2
2.5
5
10
20
Factor selected
Damping
DATASHEET
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0.4
0.2
0.1
0.4
0.2
0.1
0.06
0.4
0.2
0.1
0.06
0.03
Gain Peak/dB