ACS8525AT Semtech, ACS8525AT Datasheet - Page 20

• Manufacturer Part Number: ACS8525AT
• Manufacturer: Semtech

Specifications of ACS8525AT

• Lead Free Status / RoHS Status: Compliant

When PBO is enabled, PBO can also be frozen (at the
current offset setting). The device will then ignore any
further PBO events occurring on any subsequent
reference switch, and maintain the current phase offset.
If PBO is disabled while the device is in the Locked mode,
there may be a phase shift on the output SEC clocks as
the DPLL locks back to 0° phase error. The rate of phase
shift will depend on the programmed bandwidth. Enabling
PBO whilst in the Locked stated will also trigger a PBO
event.
PBO Phase Offset
In order to minimize the systematic (average) phase error
for PBO, a PBO Phase Offset can be programmed in
0.101 ns steps in the cnfg_PBO_phase_offset register,
Reg. 72. The range of the programmable PBO phase
offset is restricted to ±1.4 ns. This can be used to
eliminate an accumulation of phase shifts in one
direction.
Input to Output Phase Adjustment
When PBO is off such that the system always tries to align
the outputs to the inputs at the 0° position, there is a
mechanism provided in the ACS8525A for precise fine
tuning of the output phase position with respect to the
input. This can be used to compensate for circuit and
board wiring delays. The output phase can be adjusted in
6 ps steps up to 200 ns in a positive or negative direction.
The phase adjustment actually changes the phase
position of the feedback clock so that the DPLL adjusts
the output clock phases to compensate. The rate of
change of phase is therefore related to the DPLL
bandwidth. For the DPLL to track large instant changes in
phase, either Lock8k mode should be on, or the coarse
phase detector should be enabled. Register
cnfg_phase_offset at Reg. 70 and 71 controls the output
phase, which is only used when Phase Build-out is off
(Reg. 48, Bit 2 = 0, and Reg. 76, Bit 4 = 0).
DPLL Feature Summary
DPLL1 is the more feature rich of the two DPLLs. The
features of the two DPLLs are summarized here. Refer to
the Register Descriptions for more information.
Revision 1.00/September 2007 © Semtech Corp.
ADVANCED COMMS & SENSING
FINAL
Page 20
DPLL1 Main Features
DPLL1 Advanced Features
Phase Loss Indicators
Multiple E1 and DS1 outputs supported
Low jitter MFrSync (2 kHz) and FrSync (8 kHz) outputs
Multiple phase loss and multiple phase detectors (see
“DPLL1 Advanced Features” on page 20”)
Direct PLL locking to common SONET/SDH input
frequencies or any multiple of 8 kHz
Automatic mode switching between Free-run, Locked
and Digital Holdover states (see “Operating Modes
(States) of the Device” on page 30)
Fast detection on input failure and entry into Digital
Holdover mode (holds at the last good frequency
value)
Frequency translation between input and output rates
via direct digital synthesis
High accuracy digital architecture for stable PLL
dynamics combined with an APLL for low jitter final
output clocks
Non-revertive mode
Frame Sync pulse alignment
Selectable Automatic DPLL bandwidth control (auto
selects either Locked bandwidth, or Acquisition
bandwidth), or Locked DPLL bandwidth (Reg. 3B
Bit 7)
Two programmable bandwidth controls:
Programmable damping factor (for optional faster
locking and peaking control). Factors = 1.2, 2.5, 5, 10
or 20. (Reg. 6B, Bits [2:0])
Programmable DPLL pull-in frequency range (Reg. 41,
Reg. 42)
Phase Build-out on source switching (hit-less source
switching), on/off (Reg. 48 Bit 3)
Freeze Phase Build-out, on/off (Reg. 48 Bit 2)
Phase loss fine limit. on/off (Reg. 73 Bit 7) and
programmable range 0 to 7 dec (Reg. 73 Bits [2:0])
Multi-cycle phase loss course limit, on/off (Reg. 74 Bit
7) and selectable range from ±1 to 8191 UI in 13
steps (Reg. 74 Bits [3:0])
• Locked bandwidth: 18, 35 or 70 Hz (Reg. 67)
• Acquisition bandwidth: 18, 35 or 70 Hz (Reg. 69)
ACS8525A LC/P
DATASHEET
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