ACS8525AT Semtech, ACS8525AT Datasheet - Page 79

• Manufacturer Part Number: ACS8525AT
• Manufacturer: Semtech

Specifications of ACS8525AT

• Lead Free Status / RoHS Status: Compliant

Address (hex):
Address (hex):
Revision 1.00/September 2007 © Semtech Corp.
ADVANCED COMMS & SENSING
Register Name
Register Name
DPLL2_meas_
DPLL1_ph
Bit No.
Bit No.
Bit 7
[7:4]
[2:0]
Bit 7
7
6
64
65
cnfg_DPLL2_frequency
Description
Not used.
DPLL2_frequency
Register to configure the frequency of operation of
DPLL2. The frequency of DPLL2 will also affect the
frequency of the APLL2 which, in turn, affects the
frequencies available at outputs O1 and O2 see
Reg. 61 - Reg. 63. It is also possible to not use
DPLL2 at all, but use the APLL2 to run directly from
DPLL1 output, see Reg. 65
(cnfg_DPLL1_frequency). If any frequencies are
required from the APLL2 then DPLL2 should not be
squelched, as the APLL2 input is squelched and the
APLL2 will free run.
cnfg_DPLL1_frequency
APLL2_for_
DPLL1_E1/DS1
Description
DPLL2_meas_DPLL1_ph
Register bit to control the feature where DPLL2 is
used to measure phase offset between the SEC
input selected by DPLL1 and either of the other two
SEC Inputs. Refer to the Section “Measuring Phase
Between Master and Slave/Stand-by SEC Sources”
on page 33.
APLL2_for_DPLL1_E1/DS1
Register bit to select whether the APLL2 takes its
input from DPLL2 or DPLL1. If DPLL1 is selected
then the frequency is controlled by Bits [5:4],
DPLL1_freq_to_APLL2.
Bit 6
Bit 6
Bit 5
Bit 5
DPLL1_freq_to_APLL2
Description
Description
Bit 4
Bit 4
FINAL
Page 79
(R/W) Register to configure
DPLL2 Frequency.
(R/W) Register to configure
DPLL1 and several other
parameters.
Bit Value
Bit Value
Bit 3
Bit 3
000
001
010
011
100
101
110
111
0
1
0
1
-
Value Description
-
DPLL2 mode = squelched (clock off).
DPLL2 mode = 77.76 MHz (OC-N rates), giving
APLL2 frequency = 311.04 MHz.
DPLL2 mode = 12E1, giving APLL2 output
frequency (before dividers) = 98.304 MHz.
DPLL2 mode = 16E1, giving APLL2 output
frequency (before dividers) = 131.072 MHz.
DPLL2 mode = 24DS1, giving APLL2 output
frequency (before dividers) = 148.224 MHz.
DPLL2 mode = 16DS1, giving APLL2 output
frequency (before dividers) = 98.816 MHz.
DPLL2 mode = E3, giving APLL2 output frequency
(before dividers) = 274.944 MHz.
DPLL2 mode = DS3, giving APLL2 output frequency
(before dividers) = 178.944 MHz.
Value Description
Normal- DPLL2 normal operation.
DPLL2 disabled, DPLL2 phase detector used to
measure phase between selected DPLL1 input and
selected DPLL2 input.
APLL2 takes its input from DPLL2.
APLL2 takes its input from DPLL1.
Bit 2
Bit 2
ACS8525A LC/P
DPLL2_frequency
DPLL1_frequency
Default Value
Default Value
Bit 1
Bit 1
DATASHEET
www.semtech.com
0000 0000
0000 0001
Bit 0
Bit 0