ACS8525AT Semtech, ACS8525AT Datasheet - Page 61

• Manufacturer Part Number: ACS8525AT
• Manufacturer: Semtech

Specifications of ACS8525AT

• Lead Free Status / RoHS Status: Compliant

Address (hex):
Address (hex):
Revision 1.00/September 2007 © Semtech Corp.
ADVANCED COMMS & SENSING
Register Name
Register Name
auto_BW_sel
Bit No.
Bit No.
Bit 7
[7:2]
[1:0]
Bit 7
[6:4]
[2:0]
7
3
3A
3B
cnfg_differential_output
Description
Not used.
Output O1_LVDS_PECL
Selection of the electrical compatibility of Output O1
between 3 V PECL and 3 V LVDS.
cnfg_auto_bw_sel
Description
auto_BW_sel
Bit to select locked bandwidth (Reg. 67) or
acquisition bandwidth (Reg. 69) for DPLL1.
Not used.
DPLL1_lim_int
When set to 1 the integral path value of DPLL1 is
limited or frozen when DPLL1 reaches either min. or
max. frequency. This can be used to minimise
subsequent overshoot when the DPLL is pulling in.
Note that when this happens, the reported
frequency value, via current_DPLL_freq (Reg. 0C,
0D and 07) is also frozen.
Not used.
Bit 6
Bit 6
Bit 5
Bit 5
Description
Description
Bit 4
Bit 4
FINAL
Page 61
(R/W) Configures the electrical
compatibility of the differential
output driver to be 3 V PECL or
3 V LVDS.
(R/W) Register to select
automatic BW selection for DPLL1
path.
DPLL1_lim_int
Bit Value
Bit Value
Bit 3
Bit 3
00
01
10
11
1
0
1
0
-
-
-
Value Description
-
Output O1 disabled.
Output O1 3 V PECL compatible.
Output O1 3 V LVDS compatible.
Not used.
Value Description
Automatically selects either locked or acquisition
bandwidth as appropriate.
Always selects locked bandwidth.
-
DPLL value frozen.
DPLL not frozen.
-
Bit 2
Bit 2
ACS8525A LC/P
Default Value
Default Value
Output O1_LVDS_PECL
Bit 1
Bit 1
DATASHEET
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1100 0010
1001 1000
Bit 0
Bit 0