ACS8525AT Semtech, ACS8525AT Datasheet - Page 86

• Manufacturer Part Number: ACS8525AT
• Manufacturer: Semtech

Specifications of ACS8525AT

• Lead Free Status / RoHS Status: Compliant

Address (hex):
Address (hex):
Revision 1.00/September 2007 © Semtech Corp.
ADVANCED COMMS & SENSING
Register Name
DPLL1_PD2_
gain_enable
Register Name
Bit No.
Bit No.
Bit 7
[2:0]
Bit 7
[7:0]
6D (cont...)
70
cnfg_DPLL1_PD2_gain
Description
DPLL1_PD2_gain_digital
Register to control the gain of Phase Detector 2
when locking to a reference in digital feedback
mode. Automatic gain selection must be enabled
(Bit 7, DPLL1_PD2_gain_enable), for
DPLL1_PD2_gain_digital to have any effect.
cnfg_phase_offset
[7:0]
Description
phase_offset_value[7:0]
Register forming part of the phase offset control.
Bit 6
Bit 6
DPLL1_PD2_gain_alog
Bit 5
Bit 5
Description
Description
phase_offset_value[7:0]
Bit 4
Bit 4
FINAL
Page 86
(R/W) Register to configure the
gain of Phase Detector 2 in some
modes for DPLL1.
(R/W) Bits [7:0] of the phase
offset control register.
Bit Value
Bit Value
Bit 3
Bit 3
-
-
Value Description
Gain value of Phase Detector 2 when locking to any
reference in digital feedback mode.
Value Description
See Reg. 71, cnfg_phase_offset[15:8] for more
details.
Bit 2
Bit 2
DPLL1_PD2_gain_digital
ACS8525A LC/P
Default Value
Default Value
Bit 1
Bit 1
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1100 0010
0000 0000
Bit 0
Bit 0