MPC8309VMAHFCA Freescale Semiconductor, MPC8309VMAHFCA Datasheet - Page 43

• Manufacturer Part Number: MPC8309VMAHFCA
• Description: 417/333/233 MP Std Tmp
• Manufacturer: Freescale Semiconductor

Specifications of MPC8309VMAHFCA

• Processor Series: MPC8309
• Core: e300c3
• Data Bus Width: 32 bit
• Data Ram Size: 512 MB
• Interface Type: USB, CAN, UART, PCI
• Maximum Clock Frequency: 417 MHz
• Number Of Programmable I/os: 56
• Operating Supply Voltage: - 0.3 V to + 1.26 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Operating Temperature Range: 0 C to + 105 C
• Processor To Be Evaluated: MPC8309
• Supply Current (max): 5 uA
• Lead Free Status / Rohs Status: Details

The following figure provides the AC test load for the I
The following figure shows the AC timing diagram for the I
Freescale Semiconductor
All values refer to V
Fall time of both SDA and SCL signals
Setup time for STOP condition
Bus free time between a STOP and START condition
Noise margin at the LOW level for each connected device (including
hysteresis)
Noise margin at the HIGH level for each connected device (including
hysteresis)
Notes:
1. The symbols used for timing specifications follow the pattern of t
2. MPC8309 provides a hold time of at least 300 ns for the SDA signal (referred to the V
3. The maximum t
4. C
inputs and t
with respect to the time data input signals (D) reach the valid state (V) relative to the t
(H) state or setup time. Also, t
(S) went invalid (X) relative to the t
timing (I2) for the time that the data with respect to the stop condition (P) reaching the valid state (V) relative to the t
reference (K) going to the high (H) state or setup time. For rise and fall times, the latter convention is used with the appropriate
letter: R (rise) or F (fall).
undefined region of the falling edge of SCL.
B
MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1
SDA
SCL
= capacitance of one bus line in pF.
S
(first two letters of functional block)(reference)(state)(signal)(state)
IH
I2DVKL
(min) and V
t
I2CF
t
I2CL
t
I2SXKL
has only to be met if the device does not stretch the LOW period (t
Output
Parameter
IL
Table 44. I
(max) levels (see
I2SXKL
I2C
symbolizes I
clock reference (K) going to the low (L) state or hold time. Also, t
Figure 33. I
t
I2DXKL
2
C AC Electrical Specifications (continued)
Figure 32. I
Table
t
I2DVKH
Z
0
2
= 50 
t
43).
I2CH
C timing (I2) for the time that the data with respect to the start condition
2
C Bus AC Timing Diagram
t
I2SXKL
2
C AC Test Load
2
(first two letters of functional block)(signal)(state)(reference)(state)
for outputs. For example, t
C.
Sr
Symbol
2
t
t
t
I2PVKH
C bus.
I2SVKH
I2KHDX
t
V
V
I2CF
t
R
I2KHKL
NH
NL
L
= 50 
1
20 + 0.1 C
0.1  OV
0.2  OV
I2C
IH
(min) of the SCL signal) to bridge the
t
Min
clock reference (K) going to the high
0.6
1.3
I2PVKH
OV
I2CL
I2DVKH
DD
DD
DD
t
I2CR
B
) of the SCL signal.
/2
4
symbolizes I
I2PVKH
P
Max
300
—
—
—
—
t
I2CF
symbolizes I
2
C timing (I2)
S
I2C
Unit
ns
s
s
clock
V
V
for
2
I
C
43
2
C