MPC8309VMAHFCA Freescale Semiconductor, MPC8309VMAHFCA Datasheet - Page 69

417/333/233 MP Std Tmp

MPC8309VMAHFCA

Manufacturer Part Number
MPC8309VMAHFCA
Description
417/333/233 MP Std Tmp
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MPC8309VMAHFCA

Processor Series
MPC8309
Core
e300c3
Data Bus Width
32 bit
Data Ram Size
512 MB
Interface Type
USB, CAN, UART, PCI
Maximum Clock Frequency
417 MHz
Number Of Programmable I/os
56
Operating Supply Voltage
- 0.3 V to + 1.26 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Operating Temperature Range
0 C to + 105 C
Processor To Be Evaluated
MPC8309
Supply Current (max)
5 uA
Lead Free Status / Rohs Status
 Details

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
MPC8309VMAHFCA
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
23.5
RCWL[COREPLL] selects the ratio between the internal coherent system bus clock (csb_clk) and the e300
core clock (core_clk). The following table shows the encodings for RCWL[COREPLL]. COREPLL
values not listed, and should be considered reserved.
Freescale Semiconductor
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
00
nn
MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1
0-1
Core PLL Configuration
RCWL[COREPLL]
SPMF
0010
0100
0101
0011
0110
0000
0001
0001
0001
0001
0001
0001
0001
0001
0010
0010
0010
0010
0010
0010
0010
0010
0011
2-5
csb_clk : sys_clk_in Ratio
6
n
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
Table 60. e300 Core PLL Configuration
2:1
3:1
4:1
5:1
6:1
Table 59. CSB Frequency Options
(PLL off, csb_clk clocks core directly)
core_clk : csb_clk Ratio
PLL bypassed
1.5:1
1.5:1
1.5:1
1.5:1
2.5:1
2.5:1
2.5:1
2.5:1
1:1
1:1
1:1
1:1
2:1
2:1
2:1
2:1
3:1
125
25
csb_clk Frequency (MHz)
PCI_SYNC_IN(MHz)
33.33
133
167
(PLL off, csb_clk clocks core directly)
PLL bypassed
VCO Divider
66.67
133
 2
 4
 8
 8
 2
 4
 8
 8
 2
 4
 8
 8
 2
2
4
8
8
Clocking
69

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