MPC8309VMAHFCA Freescale Semiconductor, MPC8309VMAHFCA Datasheet - Page 70

• Manufacturer Part Number: MPC8309VMAHFCA
• Description: 417/333/233 MP Std Tmp
• Manufacturer: Freescale Semiconductor

Specifications of MPC8309VMAHFCA

• Processor Series: MPC8309
• Core: e300c3
• Data Bus Width: 32 bit
• Data Ram Size: 512 MB
• Interface Type: USB, CAN, UART, PCI
• Maximum Clock Frequency: 417 MHz
• Number Of Programmable I/os: 56
• Operating Supply Voltage: - 0.3 V to + 1.26 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Operating Temperature Range: 0 C to + 105 C
• Processor To Be Evaluated: MPC8309
• Supply Current (max): 5 uA
• Lead Free Status / Rohs Status: Details

Clocking
23.6
The QUICC Engine PLL is controlled by the RCWL[CEPMF] and RCWL[CEPDF] parameters. The
following table shows the multiplication factor encodings for the QUICC Engine PLL.
The RCWL[CEVCOD] denotes the QUICC Engine PLL VCO internal frequency as shown in the
following table.
70
01
10
11
RCWL[CEPMF]
00000–00001
MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1
01001–11111
0-1
00010
00011
00100
00101
00110
01000
00111
QUICC Engine PLL Configuration
RCWL[COREPLL]
0011
0011
0011
Core VCO frequency = core frequency  VCO divider. The VCO divider
(RCWL[COREPLL[0:1]]), must be set properly so that the core VCO
frequency is in the range of 400–800 MHz.
2-5
RCWL[CEVCOD]
RCWL[CEPDF]
Table 61. QUICC Engine PLL Multiplication Factors
Table 60. e300 Core PLL Configuration (continued)
00
01
10
11
0
0
0
0
0
0
0
0
0
Table 62. QUICC Engine PLL VCO Divider
6
0
0
0
core_clk : csb_clk Ratio
QUICC Engine PLL Multiplication Factor = RCWL[CEPMF]/
NOTE
3:1
3:1
3:1
(1 + RCWL[CEPDF)
Reserved
Reserved
 2
 3
 4
 5
 6
 7
 8
VCO Divider
Reserved
2
4
8
VCO Divider
Freescale Semiconductor
 4
 8
 8