MPC8309VMAHFCA Freescale Semiconductor, MPC8309VMAHFCA Datasheet - Page 68

• Manufacturer Part Number: MPC8309VMAHFCA
• Description: 417/333/233 MP Std Tmp
• Manufacturer: Freescale Semiconductor

Specifications of MPC8309VMAHFCA

• Processor Series: MPC8309
• Core: e300c3
• Data Bus Width: 32 bit
• Data Ram Size: 512 MB
• Interface Type: USB, CAN, UART, PCI
• Maximum Clock Frequency: 417 MHz
• Number Of Programmable I/os: 56
• Operating Supply Voltage: - 0.3 V to + 1.26 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Operating Temperature Range: 0 C to + 105 C
• Processor To Be Evaluated: MPC8309
• Supply Current (max): 5 uA
• Lead Free Status / Rohs Status: Details

Clocking
23.4
The system PLL is controlled by the RCWL[SPMF] parameter.
encodings for the system PLL.
As described in
configuration word low select the ratio between the primary clock input (SYS_CLK_IN) and the internal
coherent system bus clock (csb_clk). The following table shows the expected frequency values for the CSB
frequency for selected csb_clk to SYS_CLK_IN ratios.
68
DDR2 memory bus frequency (MCLK)
Local bus frequency (LCLKn)
Notes:
1. The SYS_CLK_IN frequency, RCWL[SPMF], and RCWL[COREPLL] settings must be chosen such that the resulting
2. The DDR2 data rate is 2× the DDR2 memory bus frequency.
3. The local bus frequency is 1/2, 1/4, or 1/8 of the lb_clk frequency (depending on LCRR[CLKDIV]) which is in turn 1× or 2×
csb_clk, MCLK, LCLK, and core_clk frequencies do not exceed their respective maximum or minimum operating
frequencies.
the csb_clk frequency (depending on RCWL[LBCM]).
MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1
System PLL Configuration
System PLL VCO frequency = 2 × (CSB frequency) × (System PLL VCO
divider). The VCO divider needs to be set properly so that the System PLL
VCO frequency is in the range of 450–750 MHz.
Section 23, “Clocking,”
RCWL[SPMF]
Characteristic
0111–1111
Table 57. Operating Frequencies for MAPBGA (continued)
3
0000
0001
0010
0100
0101
0011
0110
Table 58. System PLL Multiplication Factors
2
1
the LBCM, DDRCM, and SPMF parameters in the reset
NOTE
System PLL Multiplication Factor
Max Operating Frequency
Table 58
Reserved
Reserved
Reserved
167
66
× 2
× 3
× 4
× 5
× 6
shows the multiplication factor
Freescale Semiconductor
MHz
MHz
Unit