EP2SGX30DF780C5N Altera, EP2SGX30DF780C5N Datasheet - Page 102

• Manufacturer Part Number: EP2SGX30DF780C5N
• Description: IC STRATIX II GX 30K 780-FBGA
• Manufacturer: Altera
• Series: Stratix® II GXr

Specifications of EP2SGX30DF780C5N

• Number Of Logic Elements/cells: 33880
• Number Of Labs/clbs: 1694
• Total Ram Bits: 1369728
• Number Of I /o: 361
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 780-FBGA
• Family Name: Stratix II GX
• Number Of Logic Blocks/elements: 33880
• # I/os (max): 361
• Frequency (max): 609.76MHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 33880
• Ram Bits: 1369728
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-1754

PLLs and Clock Networks
Figure 2–66. EP2SGX60, EP2SGX90 and EP2SGX130 Device I/O Clock Groups
2–94
Stratix II GX Device Handbook, Volume 1
IO_CLKM[7..0]
IO_CLKO[7..0]
IO_CLKN[7..0]
IO_CLKP[7..0]
8
8
8
8
IO_CLKA[7..0]
8
IO_CLKL[7..0]
You can use the Quartus II software to control whether a clock input pin
drives either a global, regional, or dual-regional clock network. The
Quartus II software automatically selects the clocking resources if not
specified.
Clock Control Block
Each global clock, regional clock, and PLL external clock output has its
own clock control block. The control block has two functions:
■
■
24 Clocks in the
24 Clocks in the
8
Quadrant
Quadrant
Clock source selection (dynamic selection for global clocks)
Clock power-down (dynamic clock enable or disable)
IO_CLKB[7..0]
8
IO_CLKK[7..0]
8
IO_CLKC[7..0]
8
IO_CLKJ[7..0]
24 Clocks in the
24 Clocks in the
8
Quadrant
Quadrant
IO_CLKD[7..0]
8
IO_CLKI[7..0]
8
Altera Corporation
8
8
8
8
October 2007
IO_CLKE[7..0]
IO_CLKF[7..0]
IO_CLKG[7..0]
IO_CLKH[7..0]
I/O Clock Regions