EP2SGX30DF780C5N Altera, EP2SGX30DF780C5N Datasheet - Page 22

• Manufacturer Part Number: EP2SGX30DF780C5N
• Description: IC STRATIX II GX 30K 780-FBGA
• Manufacturer: Altera
• Series: Stratix® II GXr

Specifications of EP2SGX30DF780C5N

• Number Of Logic Elements/cells: 33880
• Number Of Labs/clbs: 1694
• Total Ram Bits: 1369728
• Number Of I /o: 361
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 780-FBGA
• Family Name: Stratix II GX
• Number Of Logic Blocks/elements: 33880
• # I/os (max): 361
• Frequency (max): 609.76MHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 33880
• Ram Bits: 1369728
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-1754

Transceivers
2–14
Stratix II GX Device Handbook, Volume 1
Pre-emphasis percentage is defined as (V
V
the differential steady-state voltage (peak-to-peak).
Programmable Termination
The programmable termination can be statically set in the Quartus II
software. The values are 100 Ω , 120 Ω , 150 Ω , and external termination.
Figure 2–11
Figure 2–11. Programmable Transmitter Terminations
PCI Express Receiver Detect
The Stratix II GX transmitter buffer has a built-in receiver detection circuit
for use in PIPE mode. This circuit provides the ability to detect if there is
a receiver downstream by sending out a pulse on the channel and
monitoring the reflection. This mode requires the transmitter buffer to be
tri-stated (in electrical idle mode).
PCI Express Electric Idles (or Individual Transmitter Tri-State)
The Stratix II GX transmitter buffer supports PCI Express electrical idles.
This feature is only active in PIPE mode. The tx_forceelecidle port
puts the transmitter buffer in electrical idle mode. This port is available in
all PCI Express power-down modes and has specific usage in each mode.
Receiver Path
This section describes the data path through the Stratix II GX receiver. The
Stratix II GX receiver consists of the following blocks:
■
■
■
■
■
■
MAX
Receiver differential input buffer
Receiver PLL lock detector, signal detector, and run length checker
Clock/data recovery (CRU) unit
Deserializer
Pattern detector
Word aligner
is the differential emphasized voltage (peak-to-peak) and V
Programmable
shows the setup for programmable termination.
Output
Driver
V
CM
MAX
/V
MIN
50, 60, or 75
– 1) × 100, where
Altera Corporation
October 2007
MIN
is