EP2SGX30DF780C5N Altera, EP2SGX30DF780C5N Datasheet - Page 25

• Manufacturer Part Number: EP2SGX30DF780C5N
• Description: IC STRATIX II GX 30K 780-FBGA
• Manufacturer: Altera
• Series: Stratix® II GXr

Specifications of EP2SGX30DF780C5N

• Number Of Logic Elements/cells: 33880
• Number Of Labs/clbs: 1694
• Total Ram Bits: 1369728
• Number Of I /o: 361
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 780-FBGA
• Family Name: Stratix II GX
• Number Of Logic Blocks/elements: 33880
• # I/os (max): 361
• Frequency (max): 609.76MHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 33880
• Ram Bits: 1369728
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-1754

Altera Corporation
October 2007
1
The receiver equalization circuit is comprised of a programmable
amplifier. Each stage is a peaking equalizer with a different center
frequency and programmable gain. This allows varying amounts of gain
to be applied, depending on the overall frequency response of the channel
loss. Channel loss is defined as the summation of all losses through the
PCB traces, vias, connectors, and cables present in the physical link.
Figure 2–15
settings allowed by the Quartus II software for Stratix II GX devices.
Figure 2–15. Frequency Response
Receiver PLL and CRU
Each transceiver block has four receiver PLLs, lock detectors, signal
detectors, run length checkers, and CRU units, each of which is dedicated
to a receive channel. If the receive channel associated with a particular
receiver PLL or CRU is not used, the receiver PLL and CRU are powered
down for the channel.
circuits.
The Stratix II GX receivers also have adaptive equalization
capability that adjusts the equalization levels to compensate for
changing link characteristics. The adaptive equalization can be
powered down dynamically after it selects the appropriate
equalization levels.
shows the frequency response for the 16 programmable
Figure 2–16
Stratix II GX Device Handbook, Volume 1
shows the receiver PLL and CRU
Stratix II GX Architecture
High
Medium
Low
Bypass EQ
2–17