EP2SGX30DF780C5N Altera, EP2SGX30DF780C5N Datasheet - Page 6

• Manufacturer Part Number: EP2SGX30DF780C5N
• Description: IC STRATIX II GX 30K 780-FBGA
• Manufacturer: Altera
• Series: Stratix® II GXr

Specifications of EP2SGX30DF780C5N

• Number Of Logic Elements/cells: 33880
• Number Of Labs/clbs: 1694
• Total Ram Bits: 1369728
• Number Of I /o: 361
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 780-FBGA
• Family Name: Stratix II GX
• Number Of Logic Blocks/elements: 33880
• # I/os (max): 361
• Frequency (max): 609.76MHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 33880
• Ram Bits: 1369728
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-1754

Features
1–4
Stratix II GX Device Handbook, Volume 1
Note to
(1)
Note to
(1)
Package
EP2SGX30C
EP2SGX60C
EP2SGX30D
EP2SGX60D
EP2SGX60E
EP2SGX90E
EP2SGX90F
EP2SGX130G
Table 1–1. Stratix II GX Device Features (Part 2 of 2)
Table 1–2. Stratix II GX Package Options (Pin Counts and Transceiver Channels)
Device
Includes two sets of dual-purpose differential pins that can be used as two additional channels for the differential
receiver or differential clock inputs.
Includes two differential clock inputs that can also be used as two additional channels for the differential receiver.
Feature
Table
Table
1–1:
1–2:
Transceiver
Channels
12
12
16
20
4
4
8
8
EP2SGX30C/D
FineLine BGA
C
780-pin
Stratix II GX devices are available in space-saving FineLine BGA
packages (refer to
migration within the same package. Vertical migration means that you
can migrate to devices whose dedicated pins, configuration pins, and
power pins are the same for a given package across device densities. For
I/O pin migration across densities, you must cross-reference the available
I/O pins using the device pin-outs for all planned densities of a given
package type to identify which I/O pins are migratable.
Stratix II GX device package sizes.
Receive
Source-Synchronous
D
31
31
31
31
42
47
59
73
Channels
FineLine BGA
(1)
C
780-pin
EP2SGX60C/D/E
Transmit
Table
29
29
29
29
42
45
59
71
D
1,152-pin
1–2). All Stratix II GX devices support vertical
FineLine
BGA
FineLine BGA
E
(29 mm)
780-Pin
361
364
361
364
—
—
—
—
1,152-pin
FineLine
Maximum User I/O Pin Count
BGA
E
EP2SGX90E/F
FineLine BGA
1,152-Pin
(35 mm)
534
558
1,508-pin
FineLine
—
—
—
—
—
—
BGA
F
Altera Corporation
Table 1–3
FineLine BGA
EP2SGX130/G
FineLine BGA
October 2007
1,508-Pin
(40 mm)
1,508-pin
650
734
—
—
—
—
—
—
lists the
G