EP3C16F484C7N Altera, EP3C16F484C7N Datasheet - Page 114

• Manufacturer Part Number: EP3C16F484C7N
• Description: IC CYCLONE III FPGA 16K 484FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C16F484C7N

• Number Of Logic Elements/cells: 15408
• Number Of Labs/clbs: 963
• Total Ram Bits: 516096
• Number Of I /o: 346
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 15408
• # I/os (max): 346
• Frequency (max): 437.5MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 15408
• Ram Bits: 516096
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• No. Of Logic Blocks: 963
• Family Type: Cyclone III
• No. Of I/o's: 346
• I/o Supply Voltage: 3.3V
• Operating Frequency Max: 437.5MHz
• Operating Temperature Range: 0°C To +85°C
• Rohs Compliant: Yes
• For Use With: 544-2601 - KIT DEV CYCLONE III LS EP3CLS200P0037 - BOARD DEV/EDUCATION ALTERA DE0544-2411 - KIT DEV NIOS II CYCLONE III ED.
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2473

6–14
Figure 6–6. Cyclone III Device Family HSTL I/O Standard Termination
Figure 6–7. Cyclone III Device Family SSTL I/O Standard Termination
Differential I/O Standard Termination
Cyclone III Device Handbook, Volume 1
Termination
Termination
and without
Calibration
On-Board
OCT with
External
Termination
and without
Termination
Calibration
OCT with
On-Board
External
Cyclone III Device
Family Series OCT
Transmitter
Differential I/O standards typically require a termination resistor between the two
signals at the receiver. The termination resistor must match the differential load
impedance of the bus
The Cyclone III device family supports differential SSTL-2 and SSTL-18, differential
HSTL-18, HSTL-15, and HSTL-12, PPDS, LVDS, RSDS, mini-LVDS, and differential
LVPECL.
Cyclone III Device
Family Series OCT
Transmitter
Transmitter
Transmitter
50
50
25
SSTL Class I
HSTL Class I
50
50
50
V REF
50
V REF
50
V REF
50
50
V REF
50
V TT
V TT
V TT
V TT
(Figure 6–8
Receiver
Receiver
Receiver
Receiver
and
Cyclone III Device
Family Series OCT
Figure
Cyclone III Device
Family Series OCT
Transmitter
Transmitter
Transmitter
Transmitter
25
25
Chapter 6: I/O Features in the Cyclone III Device Family
6–9).
V TT
V TT
25
50
HSTL Class II
50
SSTL Class II
50
50
V TT
V TT
50
50
V REF
© December 2009 Altera Corporation
50
50
V REF
Termination Scheme for I/O Standards
50
50
V TT
50
V REF
V REF
V TT
50
V TT
V TT
Receiver
Receiver
Receiver
Receiver