EP3C16F484C7N Altera, EP3C16F484C7N Datasheet - Page 44
![IC CYCLONE III FPGA 16K 484FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP3C16F484C7N
Manufacturer Part Number
EP3C16F484C7N
Description
IC CYCLONE III FPGA 16K 484FBGA
Manufacturer
Altera
Series
Cyclone® IIIr
Datasheets
1.EP3C5F256C8N.pdf
(5 pages)
2.EP3C5F256C8N.pdf
(34 pages)
3.EP3C5F256C8N.pdf
(66 pages)
4.EP3C5F256C8N.pdf
(14 pages)
5.EP3C5F256C8N.pdf
(76 pages)
6.EP3C10M164C8N.pdf
(350 pages)
7.EP3C16F484C7N.pdf
(274 pages)
Specifications of EP3C16F484C7N
Number Of Logic Elements/cells
15408
Number Of Labs/clbs
963
Total Ram Bits
516096
Number Of I /o
346
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Cyclone III
Number Of Logic Blocks/elements
15408
# I/os (max)
346
Frequency (max)
437.5MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
15408
Ram Bits
516096
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
484
Package Type
FBGA
No. Of Logic Blocks
963
Family Type
Cyclone III
No. Of I/o's
346
I/o Supply Voltage
3.3V
Operating Frequency Max
437.5MHz
Operating Temperature Range
0°C To +85°C
Rohs Compliant
Yes
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200P0037 - BOARD DEV/EDUCATION ALTERA DE0544-2411 - KIT DEV NIOS II CYCLONE III ED.
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2473
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP3C16F484C7N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
- EP3C5F256C8N PDF datasheet
- EP3C5F256C8N PDF datasheet #2
- EP3C5F256C8N PDF datasheet #3
- EP3C5F256C8N PDF datasheet #4
- EP3C5F256C8N PDF datasheet #5
- EP3C10M164C8N PDF datasheet #6
- EP3C16F484C7N PDF datasheet #7
- Current page: 44 of 350
- Download datasheet (8Mb)
3–8
Memory Modes
Single-Port Mode
Cyclone III Device Handbook, Volume 1
f
1
1
You can selectively enable asynchronous clears per logical memory using the
Quartus II RAM MegaWizard
For more information, refer to the
There are three ways to reset registers in the M9K blocks:
■
■
■
Cyclone III device family M9K memory blocks allow you to implement
fully-synchronous SRAM memory in multiple modes of operation. Cyclone III device
family M9K memory blocks do not support asynchronous (unregistered) memory
inputs.
M9K memory blocks support the following modes:
■
■
■
■
■
■
Violating the setup or hold time on the M9K memory block input registers may
corrupt memory contents. This applies to both read and write operations.
Single-port mode supports non-simultaneous read and write operations from a single
address.
device family M9K memory blocks.
Figure 3–7. Single-Port Memory
Notes to
(1) You can implement two single-port memory blocks in a single M9K block.
(2) For more information, refer to
Power up the device
Use the aclr signal for output register only
Assert the device-wide reset signal using the DEV_CLRn option
Single-port
Simple dual-port
True dual-port
Shift-register
ROM
FIFO
Figure
Figure 3–7
3–7:
shows the single-port memory configuration for Cyclone III
“Packed Mode Support” on page
data[ ]
address[ ]
wren
byteena[]
addressstall
inclocken
rden
aclr
inclock
(Note
™
Plug-In Manager.
RAM Megafunction User
1),
(2)
Chapter 3: Memory Blocks in the Cyclone III Device Family
3–5.
outclocken
outclock
q[]
© December 2009 Altera Corporation
Guide.
Memory Modes
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