EP3C16F484C7N Altera, EP3C16F484C7N Datasheet - Page 31

• Manufacturer Part Number: EP3C16F484C7N
• Description: IC CYCLONE III FPGA 16K 484FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C16F484C7N

• Number Of Logic Elements/cells: 15408
• Number Of Labs/clbs: 963
• Total Ram Bits: 516096
• Number Of I /o: 346
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 15408
• # I/os (max): 346
• Frequency (max): 437.5MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 15408
• Ram Bits: 516096
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• No. Of Logic Blocks: 963
• Family Type: Cyclone III
• No. Of I/o's: 346
• I/o Supply Voltage: 3.3V
• Operating Frequency Max: 437.5MHz
• Operating Temperature Range: 0°C To +85°C
• Rohs Compliant: Yes
• For Use With: 544-2601 - KIT DEV CYCLONE III LS EP3CLS200P0037 - BOARD DEV/EDUCATION ALTERA DE0544-2411 - KIT DEV NIOS II CYCLONE III ED.
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2473

Chapter 2: Logic Elements and Logic Array Blocks in the Cyclone III Device Family
LE Operating Modes
LE Operating Modes
Normal Mode
© December 2009
Altera Corporation
In addition to the three general routing outputs, LEs in a LAB have register chain
outputs, which allows registers in the same LAB to cascade together. The register
chain output allows the LUTs to be used for combinational functions and the registers
to be used for an unrelated shift register implementation. These resources speed up
connections between LABs while saving local interconnect resources.
Cyclone III device family LEs operate in the following modes:
■
■
LE operating modes use LE resources differently. In each mode, there are six available
inputs to the LE. These inputs include the four data inputs from the LAB local
interconnect, the LE carry-in from the previous LE carry-chain, and the register chain
connection. Each input is directed to different destinations to implement the desired
logic function. LAB-wide signals provide clock, asynchronous clear, synchronous
clear, synchronous load, and clock enable control for the register. These LAB-wide
signals are available in all LE modes.
The Quartus
functions, such as counters, adders, subtractors, and arithmetic functions, in
conjunction with parameterized functions such as the library of parameterized
modules (LPM) functions. You can also create special-purpose functions that specify
which LE operating mode to use for optimal performance, if required.
Normal mode is suitable for general logic applications and combinational functions.
In normal mode, four data inputs from the LAB local interconnect are inputs to a
four-input LUT
carry-in (cin) or the data3 signal as one of the inputs to the LUT. LEs in normal
mode support packed registers and register feedback.
Figure 2–2
Figure 2–2. Cyclone III Device Family LEs in Normal Mode
Normal mode
Arithmetic mode
shows LEs in normal mode.
®
II software automatically chooses the appropriate mode for common
data1
data2
data3
cin (from cout
of previous LE)
data4
(Figure
Packed Register Input
2–2). The Quartus II Compiler automatically selects the
Four-Input
LUT
Register Chain
Connection
Register Bypass
clock (LAB Wide)
sload
ena (LAB Wide)
aclr (LAB Wide)
(LAB Wide)
sclear
Register Feedback
(LAB Wide)
D
ENA
CLRN
Q
Cyclone III Device Handbook, Volume 1
Row, Column, and
Direct Link Routing
Local Routing
Row, Column, and
Direct Link Routing
Register
Chain Output
2–3