EP3C16F484C7N Altera, EP3C16F484C7N Datasheet - Page 165

• Manufacturer Part Number: EP3C16F484C7N
• Description: IC CYCLONE III FPGA 16K 484FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C16F484C7N

• Number Of Logic Elements/cells: 15408
• Number Of Labs/clbs: 963
• Total Ram Bits: 516096
• Number Of I /o: 346
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 15408
• # I/os (max): 346
• Frequency (max): 437.5MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 15408
• Ram Bits: 516096
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• No. Of Logic Blocks: 963
• Family Type: Cyclone III
• No. Of I/o's: 346
• I/o Supply Voltage: 3.3V
• Operating Frequency Max: 437.5MHz
• Operating Temperature Range: 0°C To +85°C
• Rohs Compliant: Yes
• For Use With: 544-2601 - KIT DEV CYCLONE III LS EP3CLS200P0037 - BOARD DEV/EDUCATION ALTERA DE0544-2411 - KIT DEV NIOS II CYCLONE III ED.
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2473

Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
Configuration Features
Configuration Requirement
Table 9–2. Cyclone III Device Family Supported POR Times Across Configuration Schemes
© December 2009
Fast Active Serial Standard (AS Standard POR)
Fast Active Serial Standard (AS Standard POR)
Fast Active Serial Fast (AS Fast POR)
Fast Active Serial Fast (AS Fast POR)
Configuration Scheme
1
Altera Corporation
When multiple devices in Cyclone III device family are cascaded, you can selectively
enable the compression feature for each device in the chain.
of two devices in Cyclone III device family. The first device has compression enabled
and receives compressed bitstream from the configuration device. The second device
has the compression feature disabled and receives uncompressed data. You can
generate programming files for this setup from the Convert Programming Files
dialog box from the File menu in the Quartus II software.
Figure 9–2. Compressed and Uncompressed Configuration Data in the Same Configuration File
The following section describes power-on-reset (POR) for Cyclone III device family.
POR Circuit
The POR circuit keeps the device in the reset state until the power supply voltage
levels have stabilized after device power-up. After device power-up, the device does
not release nSTATUS until the required voltages listed in table
are above the POR trip point of the device. V
out conditions after device power-up.
V
In Cyclone III device family, you can select either a fast POR time or standard POR
time depending on the MSEL pin settings. The fast POR time is 3 ms < TPOR < 9 ms
for the fast configuration time. The standard POR time is 50 ms < TPOR < 200 ms,
which has a lower power-ramp rate.
Table 9–2
CCA
is the analog power to the phase-locked loop (PLL).
lists the supported POR times for each configuration scheme.
GND
Compressed
nCE
Decompression
Controller
Device Family
Cyclone III
(3 ms< TPOR < 9 ms)
nCEO
Fast POR Time
10 kΩ
v
v
—
—
V
CC
nCE
Device Family
CCINT
Cyclone III
(50 ms< TPOR < 200 ms)
Uncompressed
Serial Data
and V
Standard POR Time
nCEO
CCA
v
v
—
—
Cyclone III Device Handbook, Volume 1
(Note 1)
are monitored for brown-
Serial Configuration
Figure 9–2
N.C.
Table 9–4 on page 9–8
Device
(Part 1 of 2)
Standard
shows a chain
Configuration
Voltage
3.0/2.5
3.0/2.5
3.3
3.3
(V)(2)
9–5