EP3C16F484C7N Altera, EP3C16F484C7N Datasheet - Page 67

• Manufacturer Part Number: EP3C16F484C7N
• Description: IC CYCLONE III FPGA 16K 484FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C16F484C7N

• Number Of Logic Elements/cells: 15408
• Number Of Labs/clbs: 963
• Total Ram Bits: 516096
• Number Of I /o: 346
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 15408
• # I/os (max): 346
• Frequency (max): 437.5MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 15408
• Ram Bits: 516096
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• No. Of Logic Blocks: 963
• Family Type: Cyclone III
• No. Of I/o's: 346
• I/o Supply Voltage: 3.3V
• Operating Frequency Max: 437.5MHz
• Operating Temperature Range: 0°C To +85°C
• Rohs Compliant: Yes
• For Use With: 544-2601 - KIT DEV CYCLONE III LS EP3CLS200P0037 - BOARD DEV/EDUCATION ALTERA DE0544-2411 - KIT DEV NIOS II CYCLONE III ED.
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2473

Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family
Clock Networks
Table 5–1. Cyclone III Device Family GCLK Network Connections (Part 2 of 2)
© December 2009
PLL4_C0
PLL4_C1
PLL4_C2
PLL4_C3
PLL4_C4
DPCLK0
DPCLK1
DPCLK7
CDPCLK0, or
CDPCLK7 (2),
DPCLK2
CDPCLK1, or
CDPCLK2 (2),
DPCLK5
DPCLK7
DPCLK4
DPCLK6
DPCLK6
CDPCLK5, or
CDPCLK6 (2),
DPCLK3
CDPCLK4, or
CDPCLK3 (2),
DPCLK8
DPCLK11
DPCLK9
DPCLK10
DPCLK5
DPCLK2
DPCLK4
DPCLK3
Notes to
(1) EP3C5 and EP3C10 devices only have GCLK networks 0 to 9.
(2) These pins apply to all devices in the Cyclone III device family except EP3C5 and EP3C10 devices.
(3) EP3C5 and EP3C10 devices only have phase-locked loops (PLLs) 1 and 2.
(4) This pin applies only to EP3C5 and EP3C10 devices.
(5) Only one of the two CDPCLK pins can feed the clock control block. You can use the other pin as a regular I/O pin.
GCLK Network Clock
Sources
Table
(4)
(4)
(4)
(2)
(4)
(2)
(4)
(4)
5–1:
(5)
(5)
(5)
(5)
Altera Corporation
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5–3
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